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# 448 germany English-speaking jobs in Baden-Württemberg

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[### Senior ASIC post-silicon validation engineer (m/f/d)](/clickout/ea94f5979a570a5a?ql=ql&sig=98cfde273b1e7b0c79fdb8c1bf2845a2aea32f83&e=3kTbxhwHTGoPjWsQHiHSEG21jy7pPTOl-2SXT92MDL7khZ_ECJgYIEEx9tYYobTsVfOlRNDPIvhVQP_LGseYrgLTD3Ur_Sxooot_Lv-crrcC7JDmuoGXxcxHZEoqOkFMSg5ZC9lniU0Qjz3KPIpUuZYN7qI_Ah1t-BIZl01unXonOqW8q9BTG7t0KqvyQs3DhB4CkpTYvzpKrz74eG6_z37yiK6a-ZNMyKEUjbwYjpqauI0nyN8bG80UNMFlmy4xQi2NJgxvr1ZLeV8bEiwkF255cTClIYahTrIocZ4L2V0AQAwrNvjYGatUkDoULSSVgoURgoRaBdnHzx2WNANX-KRwDjVHZqumwWeNDfxR5S1wA5DKomnSN8ameVjVeMKBQiP0UXA7ItybxsdAr0jObV_OV5hvP619gibvOHNv986EwlIsv9U0FcO2-RATiUHhriKIAeZLEj97CSnS2yk16Mc4DjXqd7-BIEF1tegK4v8BgVSetteQb0cJHsXM9eeS0d2iT6iWWt3Cqai99NPTYmVbN_RInY3QnIuYeOBIuSwDdD6zHzoZr0bvE6eeR0Q50P56s-DXcS93Xo8QCL1WeV46JN0gzhA9TTy9YLmFHiIBMvcO6SN6RuypwfWQqSHpf1DEYoj0cTr2ApGyusfKRHvHk6KukR7M5FfLMxlmOpipb8qJE7jhvHZSMmmwat3CxEmCeVaekjcNLdyh-SCjIAkNW7L97d91WyejFojN-RDpp8HNtEUMQW8is1pANMctSg1NKFtHh_OYn1o771tu7IJJbx3Vsh6GsPCGrjv18lEjyC3D985Mub0Bmg1fblQh2bCLvVrbsc0-7ET66Ev9qtLc53sPTDLpZh8UdcYUYRqbAyNhVlQb25wkGABTnepnYvLBcR2iAW3Qv109o4hGuIP3ooADgMcQoC_n2PDrdpYgHozESW_XHv7sVhuGoHUtF--kkKAabyNIc9aIILqQq8keMn4S6q94quPs6DMFE9kekqYShwtJlWTEt6Pr-fzRUQwtaKNXytam0AN8nz8230fG--wFoS_oCIaDuZWrf8sHSP3rt7bX2ea7cmM8w7vRC7szmWxyhLOWNXHeOg5eesImtH7LR_dV9vZwilb1jr5qpLGs3vxBunTOkfUDOq9j_n0-_MsDk2MH_4nGDWTpKHCSRGBW70IfwzBihbWYJjlzZ1Tf-BTAfJbRA8pSANzJBQ-wrgDKLwbA4DCe29EuGUg6yThG97-xlCSvGX7xAneaSZHIfgm_S4gEsCF0q8HboN0LEdOPVGl1seyZY5GRUnfTzMsqLDZbFXggUEcuZ_5jNgUPmVzXCT0li86DGukqB5Ni63BXAkaT7f_2ngFzXjFwX6UO-oBZl3BLcMhJj8LpyuqGCv6_NE_S8cRw3h2iJ-Amq9VPoDCYxWISLsHFAEAwl15lXJp-U3RJ54Zc6HQ7bcN8fI5j91ncT0rFAN6IEIE&prev=RQ7CA2EADCBEC2D8&p=1&pg=17)

* Advantest Europe GmbH
* Magstadt
* October 8

Senior ASIC Post-Silicon Validation Engineer develops and aligns test plans for ASICs across analog, RF, power, and high-speed digital. Requires BS in Electrical Engineering/Physics/CS with 5+ years of semiconductor test experience.

report probem

[### Expert Digital ASIC Design Engineer (m/f/d)](/clickout/461611ce5db20430?ql=ql&sig=2a98f9eb86cebe0b4475ca22fc09992848c013dc&e=2pS_-26awGwE2QfaTyYFtvBKHFsqO-JRoZICAgJ98m0RN0aFMu0L0SjZ7BcyQoiR8V7uCT9Vi8WJ1dnHyd7OIlVkhFpfKKUmDia-5Uu2SNUswbly7Zfq5dGb_yfz1FaqyznOhSvcKdSnWWmVeIOZIzSTuJuDBNuFr7z1QLA_TPdECDo2CT2TPQMk8f2bqiMPZ-RqP5ZXva542sOKrF0V1Y8tSaYxzEWaS4Z0FtpgqAHBd38GeGyHMGG14hIL2U-yH8GmZMlziQ0s2qTWg70m-kDE1Z5TxjC84h-2qE_bRnq38wV4t1M21QGkmFzx-udUSWrMRTnFNxlo40g5tHZ2tKPsx0YwfnuygWWpt_7sModIodSZqzrXgSr0lGG_p-0vOvPH3fZMn9gWZ3fsFIdq2Y_vU4tf_S6cOCzBNYbUXGo2cyGLY1QYI4YR0rNwR-qrWv4dYKah5RsypDAQ_JJ2gdr4udMrzf8syCMFgKckPsVl6pMt8jtU-XVGp-ymZll3PZFh1IkTfH45Wm6-J5mnkweMQ0Wn2KhMz-43urFo99EEDqSxIwV47Rq6SIjUw1YUk-PsO6P_7R-4grX4A3bQ7nYDTuUEIV8hnE6LdrV0C0O0PtEIbVng07aTCJDa4Ne2E8bI-S8OIpdkb19WuAwvGHMB0rLe4I4kcw2R__Opr9Rq7x0wYHWISGtYcdN0fjFkST43tkMyv2yVAOTQ_en0aYDAyES4YzL9XKVJLnEqonHGGnpJTZgFjyixNhA-eN1pgYpRwLylE3xzMKbnMAZZwcqzvXPbn8gy5ZcmtfXfz0oXfoZ4RjdJUZJH7PX5akxf9XLrdGwynX_HGoq1djaj9Efj2ALItbiOawY5jv6-AiQPcGpLmkFnUJGTz74823MESeOM26Pjtcae-4QeU4YiBmmsE4HfOq89mw9RvRx8My0chZYnjw0qosNWTpN5L4GN-xkg6qO7Gi0szX4J5FdsyluJp6SLyzHQJHYXlMrSD9o_6puN4tE4QnGze8f9PHv0ZPBNQdEyjKcG9OfbkRm38EacPxmGxVyowzx-LZ6OjaC297tsA17_ElV3KmZmDZD--5KD28Yt40Un81_sE3DKmeh-oqNJjfrWXIdx_ZRW6jNuD62j0t3t1NsVlbGX__AX1nuuH6Ll8kUK0PY5EfjcD2Qa5EHip1TcixFlkhL4RE-dDvneXICMw2ZTARd0OusiVB32nbh6XX4_JUzyHIoZwnHWYP8umXrlDMBuCpoUkoAyyJLhkid17zxMSrRZSlDzaeMVcHxjkXNmaQrKcsRra8N2vZK-Z8WSYFZv1Zaop8agUAuU6X0qbZFJ0nHIczDyVbRIRWOR6H3I3SM5IfK1D9-y1Hvyig9d_rIZDeWF1cG0D66Evl7AC8y-fKEmvMM7tkZUY2_8l5N5HFH55cnCxZWLHn3ln92YWCllJ0atb4bf0UdUsY2RaFVYmPhH&prev=RQ7CA2EADCBEC2D8&p=2&pg=17)

* Advantest Europe GmbH
* Sindelfingen
* October 8

Expert Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include architecture development, RTL coding in Verilog, verification, and mentoring junior engineers.

report probem

[### Expert Digital ASIC Design Engineer (m/f/d)](/clickout/18c3cbaadd3705b3?ql=ql&sig=8332a7bde9dbf8e819a3f683d1e757edd99438ed&e=n1jG1CS5nYHWwq_pJTmtK0LdLaigOCkQwzKgjM32b2oXw0MB1M8uTWkr1yIuH-20HtAGKrzjquqcoakpy4qOvbatMxxx_b8ZSCTf_-xrOSBoNHbtHDnmtkYpkU6g1qvnA4pYL03AQf5A9C6s8NTaU8YmzgQY_KFw4pXYSbSSuKlVRBKb7Kfisg_eYD1Gfx-zMTsUqy09xJ1RspV7DLVNVchxiPL6kvIfQ7hs9X-YOmkHPi5-gv7kt9qWJSGhLMQGnu2k6fG-be0O_MfVo0cv5W_KacQur7mz_ygJP6RyQB5iuhpnRIvQX_fJRAyxGxr9xdqoJIVGujp24nfQE5rrTkrqRjbyAqNmFoMtt92OQ7H8-jHzR-T2VS9g4oQNjHeVSsHVNaPT9c1B8IAhD5JexAaaeqCN7v4lEHYQG2KTKh7SL_U4OfkiWc6guSH4JUpYvSJbWfBbkhAoxcYD5qgswogJgrQ8f1deDRaq_KTrT_mNUAZQuOmLDbqAfFnEBHd8RynfAjge57PbNc9tGbw78F3Po0s9vH_RAivD52M6-rQ83TbfT-R1i83_9kTZY9OgDnti-jew8hFnfebES-5sgnmnmylRy0F1GWIhisH8QPQwCXd9oAWCvLK8XLWPtNJbsNHSue3pxROkvYwuMnx3l0VJDTAOjpABcAgvmKvLe4UMof7g1qjlphZ6z9Fwtm41u0bjzpvO7rJf6s-2pcmBzDSixcPuSPPAKYnJkJbTdO7jDd4tnUYNRzkYOBA7pHd9ftHmZrz99-e_Zep226ovfM8ATInPxUPCfeRrzBXlcw2pm_iPa6TutWNCqv5vM9y0rF8oqk3f62NiJr8UJcodzfjco5OEbvuDM204KVteOSFoinH99aGRTjWgy1BrywxvlQME8wMLLVXlsFBmKUE7wTq8w0-PQ8jbp0mOVGtQRN7NGa3K4pny23zyQfC6Vfyb9nz-e7702pWrKzyrYN-qsvXP-7ytp-MAdfI7PYeMebi4TKHNWFN2B0oMowhKn4EoGeHPkKz92VOqpNFqM5VLef6q8mlRzBqREaNzMI8hu8LLCQX_9_9rYanGA5jNTt_31uTgIwY86ZR8vUdBQlR_8OiPjoFR2AsjuZ53tlAzTDnAuZqU6hhLE7O2z87JpVQ70XUc9du1hAKT8celHrHvzItvbBf-pT-Pbkkcyts2nNzb1YVSuczZKTs9oHJ42fa3_g_XdHC9acyntqPUnj9Ucury7FkbA3s2uJbVp9d0UpgsDVhRKUj0b3lh_RPA44_WTPnxQYoNKZjIHJz8BfwbMDwW5H7utwqaH7qu6RAQu4w2uxiUWWz7OADqx7W3Edg5229UEKfKq1irjUh856en1Nvsfmy9XD-2ozmjprolyc9cuRAHbciKdhUt4sICUEmvlQemtcBU7w_Ku-8e6MMJhLE747soVTt1ac05mDCKcgsOWT6bOjpmYdc&prev=RQ7CA2EADCBEC2D8&p=3&pg=17)

* Advantest Europe GmbH
* Ehningen
* October 8

Expert Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include architecture development, RTL coding in Verilog, verification, and mentoring junior engineers.

report probem

[### Senior Digital ASIC Design Engineer Synthesis (m/f/d)](/clickout/51d617cf79e2d622?ql=ql&sig=4d2a54ebc02b1d1e9aeb5f50ed75500650d2c5b8&e=NCxcZHEd3EzvuaydmSQuJJy_iTn3vXuiQlajE-gFH1e3wCfmNfBjUHEgQyoHQuQKvHL6fdZ8artW74dDbU2uoEy0bbz21DKNv1nZnOI8CK-cfN9EfzxmlES5NcmEhWl42IE4qgtWhoHUpIn4fL-bUYJdobO7gm9KNKpCvX5fZLjGMO57o-w3_tFC9NCl46JDvyB2MtwHeBHmRaR5qQuUVWkZC_H_i22SeIUOA_7-wF14N1S3GYtm7DHxZOYe-xncDT8HlqTDqBPRcffUfJ-QJDWYor9lAVKsW-dPxNoqCa1B8b9KS_g5dxHntWlgXtAwYh_4gLmvyg-BNMKKwi8PTPuP1ncPqIRmkFC8Zgw2qqN5dS2Q3woZ4LfvxIsFJL8NMs6tVRQHpsBfOFFzi1Ww-Z5jIH72VDO0Q-MKLfoI2ohxQrP0aH_YRCwGWURFm9ae_wPIbXnEYVi27jI9H5n40rC44uRra3afT4E0Kt_zPOAYvduP7aSsdpKsPeKWeTVgdcruDV9DGx5YgFn8s-UOgU5HiEyoo5PkGZlKRSgIqNosBxrEhISQoNOaIBFGiJBWcqDvZ1irlKzoe4KdZjKVeIb4Rd2VtwxxbRRPKLSjIHnS9UB0AqSqAhFwHrE9nKUA-i_XU36796CXqDVUZDlJqpT8Gl8gHoQs50C1Ob_u3DJWT6E9jpMSUjEhzKQeZ9RX8JVROLKbMUxUg7meeLd-X5oSwFiWu4ztKAcklufGvRkhTEIxUyASbiXHGOCGzn_oZuI60GNxTY7c2BX27ncR7GRXC1fz0_Je83J5wOKFgVr1R_Tpw02KyfrgfxwpEO3l01j359TUa6LN-PlPBnwKScMhcnYHoHf-0zcMMyaBiwrO3ikMtm7otfOI1h_G3k_dV_6WsblyTBLTGqa5W--QbVHls-5Y3chw5XbALNP0EDZ6SK_X1Git0VleJmsm6L_0iNRtb97mchl8K_O-h85Q4B1vty5UKc9v3iYyXcE0fuICXkxzkAEMMYbjnDTZeezlUmCELfbGSvjADdygDk6U9LAYLoCyvVKldFOUAuXcr7abkkvVjzlOP1GqTSAnHnrt-S58WaQzbLBF-j753MEP5h4-DNqXEF6iMVc5HOPVu_P4ppr1IDqRKLh3fhcRiQEVrp6i1CiYaR3sDFoMc_0zV4SRt4W-U2ubEy6fVNzsohJgMFtbidvdU9J3T1dVrV_2yHjYr2s9wyWO0DH7ii8T_t08-TgE-rD3bsIosP7Dt9ESG6fi_t0aZ2W_zqVP8MXtBDJ4k_1NaSgtXeguZuQMgJWcUHM0WwaY-Xve0VRjnqZ-ih1cCTKDRa1d0tQEz69O7NzvB4A7d04QIqYXyAoX2llX90GU-KvrjDHA--4V2G5_qLm_rmzkbtiahqkJWrivd4aYJ68yh2-HzliOZPnlPIYD2WJNB-SIC544wtxhO3VUZM9X-mjFbHwvxKoO3SJXZuik&prev=RQ7CA2EADCBEC2D8&p=4&pg=17)

* Advantest Europe GmbH
* Ehningen
* October 8
* part-time

Senior Digital ASIC Design Engineer Synthesis role involves creating next-gen semiconductor testing ICs. Responsibilities include RTL coding, constraint generation, synthesis, and analyzing timing/power for complex mixed-signal ASICs.

report probem

[### Digital ASIC Design Engineer (m/f/d)](/clickout/37c037ae79932182?ql=ql&sig=2fb3c537bd178f63ae9c25d842b369c384841df2&e=dCQLWXBwO2MjFvKUe08RqpBpwFD8_-WveTFeoTNQLX4K7yV_CeVNA2r0MKIVPqWebmvdPk1dyIEZMznuSv1bM32Z3Ib32TXgrdB8RlTYm2zv0x0qcq3eJ-2Ors4AcZeOtSKFzJUXSxNx1Tk3kDgW1XySL--9hQGt2G1oDq4XWiaW2PPOWGXh54WOj3D2P_eb8hHoeRWTgyPRUu_IGvzr7HE_Jy_Jb6ZKXGh2I4fAMhuekBclMnu8dgTX1Kmq63HxijakgtxzNcQkiE0_Bh8QsMGy-mG_QfOdu4c-93oHdBj88bJhlr-kqlNFBa2BBtCKFflX8gYmxWZHWptlpm5wDr6SIKwjTEB2UAw2wWXn9RIBWp4v5hGbrCWbahW6z84mpgi8pF3kGMBC_UsVCOa_mCKzv9pNX_rxRukXuHJWFmUhXdNhaI6afsEXlNk_QnPFMLXZCOUad1G7-MbDryvo4tTkQis8UvrFGb0Q7JJk3DKN6qS41UEZW93tr9qLzD4ABSoRHYSRD26AYSHO6XKxOeSsii3PuVC3xAtwaAWu-8hc1Zyq-F5r_F7Rl3gm3rV7lMpuZOeeQ8lb8AxxlTtUk3mmuTaQnu_wa3EX3Ig0Eig-3y-qHcY2OEKzbVtCuEf5bwnZoUB8CmnH1ZEirbKtiLOkrqArtANmKhu6xMRPkc4DVcwYJMIjNL7Wi3fQ_EBhXzoZ63dfFc_ZmKBxp0vSevoC1DIMPtAa10p1hI1eTnB4An-l3gEpVIvuPJdCuvaOsGG-DLpeOZWVb4lK_IuEhdsj9nOUN-BlzjaZQPC6xbksyMMnx93cvQLEztC6wnTvU_4jOjzyVFe-mKVSmj94LFa2Ukyn7OHKW2ry8ihtwbv1dvEjqXzwmPtq2vfFzBvw6pUhAeN0Uzc1HHzCtk_kKrsPLkFZuUMXNroOdhkUTLfk9-IfV7IyfKc7uhBXJc_RDLWWnn73HfNxgjRfHE2B_9v5bQpcVEiWXexIhTk2MFYIxyPAW9jI-Iyc4R-3dBYHMSwHdtYBqyEllWteJDA52ONKwTJmPOVqnoJWctyF3H0uCyrVIdztndTxMU6_eHr_20MY_9wQdD-Ep6UALkwXmgKCU_c3ofa_x-4XDbUdrl4HAFUQrnw7Pi8MooLmmC_W6lteg1mRX8yj1WuMGsWDZ7G7LOfx244CtXFIS2L8bhPbAoao_dZNdfJqeN4lhFExuF0tS79RLhQHqCbD4D7yhK0ECGBBfbcvjzMHMFyLcTC4vm2hNInAXkmvs2XUY5zNptxCz6L9XfIHlW1MKA-lND3sXr_mjlN_E0oF2EGVQvYitubQHQCv-keOAQr27UvqVhum3XocO_7tl9g1RLitl9SUsxZslmVvhU14wvdM-ncSHKnXJknsXqUU--swgZPUwjtp_GdudW24vEcjdkSqqLJGsW4-StFOrH9mLXCb8E6Tcw&prev=RQ7CA2EADCBEC2D8&p=5&pg=17)

* Advantest Europe GmbH
* Ehningen
* October 8

Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include RTL coding (Verilog), verification, and end-to-end ownership of digital modules. Requires EE background and digital design experience.

report probem

[### Expert Digital ASIC Design Engineer (m/f/d)](/clickout/8c43eb32fd7710a7?ql=ql&sig=6d1348a76c0a58551b8849fbf190d4cbf598a7a4&e=5HrkF9JmAFGPwmnwSQFXthlaqJPOIrMdY-su0ZeLJsAB7r1lOQ9X1oVOrW86SdtgPVNrjHDXppMVKFOddt7udo46zy5NQQHApz-GP3KPewUfrlLiPP7gXJ6senVoPa6BEv1gNlmhU0UV4-2XT8K4T1pEypOu_2QUNA_06t-gyPfRM71ClIqyr5Oy9wjA4el48ezjbXuIoMx0xd10CquoHwb8SETgXmGjCR8ZPrLFnaqiZwM919kZ48SPw2x0HSGo_rxIRRuMMsxobgg9vK8Wc2Psayn2bKf1jwWDqbYp1O9Lepm53ov0TKImsZAPPY0Ukntw2cF7SbgC3EdytQKgRpdhAQJ-tE9aAgxBCcoM3UIMq0RPz8wuSXu6A-hZQ3YAXAlTSHFKjiOI350uyDsJzXEqTGscuAbgQ6qjJDDwVuAHD0chvP6sSfW3X8HAYPeYwbHXpfqt4kXAkN4NmMg1TJs4dbtEg2MlQ-TfLNP6Tsg9-2X-bFn6SoMcs-OjWyGSDkcdPXUFV-z-K4I3tB8hQi-ozEa1mJd9uIgB0mtXAh915Nam4DOK3Mve9QPCw4HluTTpAPlMQW7aeliglhK9OwQ3hOzhZ7IiXH5ig64SrsfGTK6PNOyD5A4AWfKIMgP6XHzEEhys8BrnVHZhOyWUIRSphKdcHjRL7fpqq8ddsRsFDUAiRnnY2EebRslv906bktx6Sr8NQtk3zT4qXZ7LpxtBdc-m_Qe68CjsB4OtKPOKN_hZ2070rpunLsCOXVxYH-nWNk2V4E4VuKiYzbp8vo1c3v0XPTjZ4_TyGJHQdq_q4dRyIheh8Ol8nlWqDipqkX8nP8cPIHIwFHg9pacGesgmbmEdddehP7JJcXg4iQBZjd6d4-7jK-vkdYI-uYBMQ-lemcFAkF1JE4HNxYY6HPxmK46IkI5J9lW6t3wvFH1obQF1jeXgeblZmlt-UmQ8NqHpYWG2mBIXMyj4e4wwa6-VGKws7NBVMa3BSycIFtxKp_VCmfkj7OkQTf9wp40_2GaQoKQ45g97zXV_I-ZBUshuyJHqilAsBTABCS9OKkRz23V2Z8DeocFKSuTjoUghg650C_KXNkAFEkQPvIhlU7YYQDxDYSqEYqaRr9RsQSUrcrOzUQJKqg0C4HKt37wznQu0Nnjj9rKS_mJUm18OYZJhpVXiwzGEM9B2GdX2jn9kSjh2yBUfnVxHnbRqGkCLtidyGrlH1uJUAxiXhRvqDpdud46ip2zmPaFeQQJQ141p7voH9Xfx9EAyxQfV_gOJ_b3SCKh90FRe0DZptfrKGx-5TnaetYQOi5GSU2TI5eucepsUKwvhjFTUlBK0GV2pgjcTYV3VNtjVyEb9Ic1ptL1yZMnKnKuDHS00wdjUxtmHxMjTKZ5KV_7ZqPdW8ime2g_Dsxlrp8-zISnN_gb15ffp2MOnWG8YYRr7_XfR93TshUoOv2MMrsCflHJqgtA&prev=RQ7CA2EADCBEC2D8&p=6&pg=17)

* Advantest Europe GmbH
* Schönaich
* October 8

Expert Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include architecture development, RTL coding in Verilog, verification, and mentoring junior engineers.

report probem

[### Senior ASIC post-silicon validation engineer (m/f/d)](/clickout/3cbbf1ebedb7152f?ql=ql&sig=041722714806259684161b56007d6149f177b4ef&e=Ls6JXBQ_iu6Mn14Zg25ZOjS3-4cF_vtbGeioUGYnWuG9NRVBYkpwvk-noFJm7StgrgpxcIVCfRKu7dsWrkjKA-tHcNlreD2VMbAFBY5Nx-HiUWGIOjD0GgiAkiLIWNuA6Rd909dlgIDoaVDY6cWMsExJgv51z3hCV9s8mvjj5_t73ClF8NkroatAqdmUxQYHtY_JwFhNb0d-KskhgIy_y29AiQ4MIDXPX7Cl1icNy2eJOvLWE6b2-uVgyLnEcDUWBWiN0TekohRhmKw7NyBPvRqkhYulKQOWgCZzKsOA_jp3R4YjSYNvEqCabrdwEEelaNHVPPZKG0g_KxyMmvkLbCdMfeZNX8tNHQVG0TPKwEn_ydvogqfC7zznFTadm26cePQWZoACkMFhj24DCxU7b0cgJd0Q6avVIg4mJWr9r6Q-7h9GtUAs0cGhjP_ILq1SXmYvmkjvGVxxVCGVU9AYSIC3Rx5dmeEWDmELHWGqb0zOjMl7-bRdTLq2ROqBDWMeHj5uOFUNoGA38mzlcJgAGS0bLvLC_xwfOJkDYxTC3mnDAc6SwMNehaGL9ZhPqxdwWUemfu0RV4iPdB5zOTSN-ZVXawJlVihUGODGtvBZ0tCcyzfnle0E0pyMqc11hMCEjmV44lbPFsCVcT3Qv7YeRPGBQ-d4JDwqqDLWq3bniAnCfjolWuzgd4cI4M5ZdbN-vyrE084TXTdPNBRVa9FXTDS53en6qTnzFmWubYCYMlE3nmVqHaGtd9qHMcsp4GaVjlESEHhDrCnvB-QdzZhLh0RkQsptGE05McRE4V7i1Q6DHwqyP4Jxhn6LlnCWSWu4BGuGeor9ach0B35Rgyd3kpMEzrb9hkovxYzt9bSCCvfvBCw_IySY3E9h_wn-_BAPknSTgKYicLbFsjDke47xEER37RzoFZO6B2944dQOC0uNtOO8AJ_LSbbU3V4OccXdWdw3FAbhHbaqAXnSigw6Q0kbyX_UTbxsTk40Fi4TcNimXiSGOLHY7yksaBH801z9KBoKBPl2dns4DhwEZT0RjmY0CVWnDG-zgXGwaEQxRSmmXgu3a0NgJQka3VYYAuv4Dfgx9AVNV5oRRAhTbWHa1h8ZF1afhfp81DdnpERCKl4sStQ5DKzW8punNMZHtcU0QIF0hrDE3AONCJvkbCWnD_QBzWjsuntdzt9AQtZadYYAp3o_OVoxNCZ8h8OUGYE_8F5a8PSTZ0telt93A3C7ltLdISlqS8SWW4YOAGRKn-V5KJeW2WkdBFIsXKFdEpIlO47xkbtKO9gvMnDSYwVc-1ET8c6o_1XxgVf8j8YBFE5FamRD5ls6ROeANf5w7aaOA9mw9j53Qvv7IFJJtoyqrWuvdCy55pyMh97jzg-CgxS-EUEAyL3MY-cxWCICkFQhxk4oWsDMfqn7MRvwWMfO-dSV-3FmN0rXxz3RLMBdS_jcMsg3iTzrpkxaHcDXdrv2bYHyZv1YDU8&prev=RQ7CA2EADCBEC2D8&p=7&pg=17)

* Advantest Europe GmbH
* Schönaich
* October 8

Senior ASIC Post-Silicon Validation Engineer develops and aligns test plans for ASICs across analog, RF, power, and high-speed digital. Requires BS in Electrical Engineering/Physics/CS with 5+ years of semiconductor test experience.

report probem

[### Expert Digital ASIC Design Engineer (m/f/d)](/clickout/760052c5cdf295ce?ql=ql&sig=5f7c018059190b9fd6eaba6b138ba372c96d945c&e=tDlTAQIrPV0agzPZEes-7VwBiMtNXDcpY3lztGl-fT6RQ4YGzuU4uXDyxCwl1Abh34nTOS59deI4_wx0Bpq6NQ64SByTsxk-ZhKLjHPcT_Y5VOD5ADKhJwbqf7ZspRMxoZT2C0TbPqaeLTc3tUbDZZj-oY7YAjpE7NX3H3v7d4JemIBAOlV7ryPwu_7lRXEdbO623V2SkvXN89Xc9n7b-NoLvkyElYsvM3p2v1eQAMa-Emg46qMzZnzE65oG-fpZq6pzMjce2mCfgsL5yGkWcj5ctEuE2yPhL41WIefcz3yeAXXJk9dZ7ynQJ_h-5YT7UnogptOC4-garuLj2LG8tH_HDOanR_NLLQ5T-BHhnZieUG94RPDKdeB90zpfKl_Bi3XaXI1lJYZi_oMjauMj3RLAieaVApE-R4JHfCeHucHDZ6LihkIRPn3-eq472nLGg_rRlpe9L9T94eTF4Jll4zLc5x70RSDIEIrrL5x-9MmC0piFZTtvWKyOaMryx0ACfFXfbjVXL6J5YbzXMgdvitgRcGcBfr1et9apm4PtJGCxYL7j1kPtmmc129oTfLLWFEHc_8LVcGuUXxwHx2n25XbYRWdgYNndkmJeyal1aD7Em6XKuKFWzrHGbC4Fsp58avh3mq5iJ-vFihKxcwk3M3DMSg0GFYoGVlFkzmeMiTa5sDs6UqZgQ3mhmDWkDY7xi_Rq7ZJPiXyo7p1aPcpNfTnN7-2yE1xhMct6N4zNczxHTLJvr7b58VbCqdR_O1shJVoRgNRckR7A8FtAUPkvxHKJPtK3T0pmFUzBs5TG_mKD70nVflSxVcIRIrYhJNd5DSUQHUApY6-EC7NJLUgWGeSj5x4Q5l8W1bKCFhyVvz_Eg_94W13EoXD-EpmQlW1v_H-Je8E2OcT4PJJhl2lX-bjPCed5DxHpr94tcTkxQLIbpwbX68m3TFO-Lnxk8CL9JeY-gFyPSAVaMFEOfYlYNX7Gu9sm6HOrMWooCl-EN7aT5ea0btyvBtDOfx6OhPLt4F4gnoZoQDqC5yr9cpUNrmrGNSsdP0S1gTHXIJYrcRXLQ5NO8gyMAudS0BOCtq4qhB2QikeJDOVEzoZKBuhspLRi7BYb988CrFh8Q4lrDMAzf7w7PooJ8T02Of0qXaUrHCWY8JqK2TkSLoli0hM1uHZYg_DG524k6P13oT-NbWerQpPmv5Vjoi4s6K2k920Gd5lEtjAGpf8jV2YP0uMKYXfP7zucT-Dbz108iye9v7HTEaj9H24lNlkkpSGVniOXAomyLE3aQ3VXGGp9IMYiDGIGecOcto1BTK_36MHJx_Ojf19PLzl40NDXDipW6_z4pZI9CkGaqwplEspCQvwlpgAgcLAvZX3DSIVS3r11biWsRfGA8w-6v1KN1xhoWOfbnVKOMPPayPAZ9Nylp7etGWWrPz42m3xPgbbQJ1mJpZ8MzWnnHEH9T3-dfoO2&prev=RQ7CA2EADCBEC2D8&p=8&pg=17)

* Advantest Europe GmbH
* Holzgerlingen
* October 8

Expert Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include architecture development, RTL coding in Verilog, verification, and mentoring junior engineers.

report probem

[### Digital ASIC Design Engineer (m/f/d)](/clickout/80eb25f1a6844e28?ql=ql&sig=5c8ae5b9b7a755d9f68282b2821d8ad5525cbb3b&e=G9hueoGml0oGzmawwXsfwEnRW465fgcRNPxRSUsAoCTp91gPfVfbnINx6Nz8NMFH6pmS1CFwCiOZO45DjgDp0MeS7n6FFKHLf1k-Bk3wC8-husEM-jOg3Y_sODuz_kxi8cyxyRsufMEr1Q1DW_y_R4GKASOPBzGgknaaMVv3P7R5K1Ko5-2p7RNINS9oJn_BIK_0STQWKuP87Hb8ymkAg9uk0Nkoqu9uEYMrtEmoN-6N-jUwv518r6Zfq-LVYujO8Sp1ewjACa_mtH5KoRaKx7imKPpAK3GigOMgVJotazDjh-HtB36tV8S23Wvtum7ciolwU6aM-raymlnbvoPzkQTlSZrZjA4h2-GOVGkSedX7n35bc_GmXqUoSXXiKqthZyCmvS3v4Atlv4hmF3ync5jv6_4hcfNuK3ifdP3cOmL5v6Rf5GsbNYjPKj690CuO_Ko-sVK4E2naw9XvdGXE3vHl3apOpA15mRj5ZIsK9G4ntK_k-k2u9tOELOMYXjiecVPY7VG6NZRXb6ySqHBtnBi2oxF3nzpEcLLPV7rDAH5knHzEdV5jjKsYZhtjVdmLgWJjsVXMf5uhcQxd3knYc45h2hXHwdT7GTO8m5rj3MgT8WVl5dT7xhya5dMVwPgv59nxJSX2EZsMUIq4joyVhGnMvHTs9VRck9WMG1GUBSa5v2fK8VrraUqa9n_8bgSl47a3O9Ws_zh8f5xLGU5hMyjR0Tuv2cyrlXd03jOPq8_2Q3z-8snddccgUYuzh9krb7MuqL9s3N5wpUg0m6NFnRjhoY4HLFRmxgJJfH8ql4R4sjQNHXQMFyVLxiooY_TUVFdQxyLMYzOxLnogwqS760jSrqmtwv9AQ4dlOjX1001Xndv678MhhU3_U8CJGKIKVS2umR-5U5Y1aqz3XgS9Smy5U87LYwWV6HPdkk5I9bd0QVuKU_sc_pCQr6-W1ZpArNR1xdO3wY-f_7P5U-tV5-nS4O0GWawmC5lWCCIICCzdmyQ_GZlzqjhFgXdT3MH6v7y_UBLV86ELmjV1vuG8bYRWhmqnSXWOOuYMtGZ3tOrxfzgJiWeFA_0qh5N1EyRbzmh0Go34DUSdb4ue9YebbKy3Omv3OsH5FSdJWkuxRHroU6jQ_i9ErpqkAlo--ksigEt7B5cChdaU_72ewGPSUZiYZsNLVcao--7-q3y5Zmq4DxW7TTIy7OyrnsCt0jm1fCz5B9t9Gq-acA8nQkKTbEskNBXbdJqt5btorB7qLyySNwTnJ75rkeNHQwQXAM3yY0SYJJTAStOIeAOZBsIf4y7COYeIJa3woEYx62AR5BKj1NHz3WNDdwYdtPQFdWcNMs70dD0yrBCOwPryZSG-t5i_xvo8OREhDpze6OuSeX7OeJI7Af6QHSdIMHSsRFQTkiWRoK1aqqzCiI8iRWji7Pb2w3pjB3GUQgHpCuaSOYz9Gg&prev=RQ7CA2EADCBEC2D8&p=9&pg=17)

* Advantest Europe GmbH
* Magstadt
* October 8

Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include RTL coding (Verilog), verification, and end-to-end ownership of digital modules. Requires EE background and digital design experience.

report probem

[### Senior Digital ASIC Design Engineer Synthesis (m/f/d)](/clickout/e8caf311fd257fd9?ql=ql&sig=106d720720324fe0cc5b8312a04e56c7a49796d6&e=nbNe90TjtJgMShMDobGcbvQlJHmOZQnePaibrSLqHTmhwhk1RnqhjRSTvaNEdm-Bi09PjJHFRa6Wo7yhJayyPO4ypTDeCJ3dOoxVq59HLNfFaGT11gw3vFJOryY9HG-9JBYTPk_1rCLnLdc-IYV6GfbJe-fyeVHTkg-wr06CfL1Ta8bVBBcZKmXbuq-Md5fRWZ_71W-uTzWqAxkgkCT8wvNYHoPQLNYakiyGOkpe1h2fMSRIzc7D36Yo8Vieh6QYwAIEuHDU5j-vjHrkUGPOWYt4pR-FMUxsDh8pqcwKuCqa1f87iMF8FDdIwGtIcWetM38lPOxsa2hlL997nDaY2QnSqxs1YgDt2QX1r7ersrvstlvV7bSTFkhQ8YRr5yqIOc_S553Xj3b-a4Rmhy1fck_BtTujkmU0ruJvoh25QuflsFOyHHKgpE3ox9Im5OK-6mYa_pbhV8i1kjhOlhaTfsSIwWpc5LU_5mc2_B2pfpm4xD-YYSl_6Ffd7xizQrOf7-2M33yrddoz8AEX3T3MNlKA9YAddUU08djweSrBGveyxPG5Gzz9iMINWsrak_f-9IYNfdzMhPYbBhWkBq6eVfsdfSGSUtJw0xqaWkP0f6hXx3FPCowpWEBb1cv_DdgIWylmGFr8IAoC2J5pGSz7VHxYTOyOKzBzZ_wQZ6U73wezY6ECi9ZlHApLsDnqAbbURoCdrcVXg5pR5nlISnCEU4j_r-rkHvLp0kEtxa6rOBTjRjTUV0EX11769DaeakXNw1E7arBx9R2LgSqeIqkVxeUIkDc-R1cjUTfIetcPR3WH3yh2V48Zxd0SnEGT_WCsLUOFETd3HHZ3wPwvL9j7tRuO_5fRECQcwlic5agwkQZ44d07j_VAhB8RO7Olg0QB2JWmElWAyzwcEc9E4QrPVe2UQ0o43mEdJyak94jP8xlyNICz-wvoaSmTPqu51MyRMGd-qNjRBQD184VJoyhTJZu3ZTLd7rmAmaJzsjnXdBb-0Kns6fXXdbIt0vitUOBvL--RuXibvYQ_l6olLI2CIx2xxTArPy8zS-efcixn1_hIUX06f3NR7dEtI9YtjyLdunhKfko-SPY5MsHym19K9hN9yDeUmJ8Cyw3oKneCfd4Cv3vP3MOR2kFkcH9jwM7kg38DiAKYfvkRYhQ3kVYKRXJhN4iM5vtUPGI-5w-p3zu55Ryc_-cdBLb8gLdP6ItWM5liEOnYmaiUReCMnswp6VIDcGOc40_YhPpiiALWnor6oDzR9eRL0scW_Gdm7xkSWy2tmuFtC9fqTUg9D3dsRR9_Xjy15Plf7V54gUgwtgPw1nz1QrNpWTFGvDLChR5W60zmpLKCup2ArARL0HIvz3Pf42z_QroWleqDa252l80QFWsG5WUS3YIdGJ2FhLv0n2yd12q9b4M7IQlM2UantxESe87jpYM2rhD8p9oSqHcBOynMexc5bf-FLT_UPXhsgqIZJDPr3cY3&prev=RQ7CA2EADCBEC2D8&p=10&pg=17)

* Advantest Europe GmbH
* Schönaich
* October 8
* part-time

Senior Digital ASIC Design Engineer Synthesis role involves creating next-gen semiconductor testing ICs. Responsibilities include RTL coding, constraint generation, synthesis, and analyzing timing/power for complex mixed-signal ASICs.

report probem

[### Expert Digital ASIC Design Engineer (m/f/d)](/clickout/38e285906c19e3d3?ql=ql&sig=3580d688cf38d936b692e1eb84796aabc581db93&e=OhYL2FrkQwaJBB02Lxtex15kvYSX9dCcgZMrIbIW4vF9obUjS6ZHaZUImjiQwpbxpcm8bxcMb4YEAHdPyEK9xr6SZiA6V-toNiwcNu-xpEEBQNb9LZNYcoKDcBmBJP7zc4mPgIkfN5pGEafwbyy4o-Sp_vPVr0YpL7znKSo-kVGzEWLLJ0JghENpRjuimlBb0ErT341me7JnyY2ewMIbUHLE1Ui-kq7SXG9yTyOutTs1YYGydseSVHsLn-k81mVkBSxIAr_yvzzQHHZIAgkyOxNMjTZUma6kFM-VmVZKDupFPmSX5IGoHguOBC3AiRT2WbWUgkytBnD6t50hoS6LFqs0o7nyjTok8FWlauzl-AoSR4hRUDg84pjofYP3FAkWoOMlrU-jygrJA2LWcZ30kGtc0O_YpQy0bHNoSlcLA25uuflkD0D0dOeQOhIuCNtaZiy5CMspgHCBWIJlSPGXmv7fqp-LzLQBmhP5zVoVI1MsH5-juTg5uxcFIpnkjZBnbuszot65ghxseQMJgducW0VAC2f0dplhXWnykZ3QTnc2czRqdG8gspTU5zthQjAv3Psd35vZb9ulLvUePRif0CBRrLVtHfSRPwdJBGMBKTzqTfJZ6hdbkdOrN9-_9sl3f4KoD1bVVQeGxE5xWDI9FkV_3RoYl6hVkRiuQRUahg74ugaH8OOnx4O4Yabl18GS52nZOMaBEoQHX5M9j80hqvtTFwgfn7hs76tyJCKn4H5gQSdOx2slAJ1z-56YOMbyAqkL4LxBEY8qu08KhXUhh286g6306cSRudj2mhk9s4U9JrCItA3EeRkMv4gOK0Nxx1DH3M1mJ8kx8izeDovuBoqVmN-IJ3CXFjCt-QN4l5EkAu1JrXU6F22x0_R0z_oJcrOYK1sQatTfbK-KVNwuKwbRnlTGMpS27fR-1iXvd1lkS1nHouZ3rZ6OOtO4fY1cq-fdhNKKWnOEgCkut4Ii66-MSxm6_76QWIBnPUQPhWDBewBDJF9ed7yOJZhj7f68v_6om0w_VHA24xr4G_YjuFTaUYro7BQ6dZJ8HfCLfWNBERwdJhfcrogErnzwM07K99lDk6aP2W03FN1PRTG979peMMC-elumx2hMgPsJks9N0s0d_lfG65NEowbJx7tI2Cu2ayYRCeiUOXHW6WIn2vFenYmoeTZVU0laNaQt6wjKjudN5gVYmbVAwZnUkTz3F5H777IeVnDczld9SfK1yo0n7TXCIqF_g5OW0P3EY11JtCEWOdSZBdKkO8Xy1_ML5p7PyDQgxAGZED067gUX8ZY4ATmSewQjFIioeDf1e2FDVKiUDaWCIbtJblHyskr6iNhkUleRQYWjTy9_EES34SY3mbZ_fuomTOiRKrqqRWADZcql2x03NEMLgvA-S12q9LrbImf05JgltVnjZzSI8gAkUMpcfPE4QV4MhAcgIfkkhKXzgEBplgE&prev=RQ7CA2EADCBEC2D8&p=11&pg=17)

* Advantest Europe GmbH
* Magstadt
* October 8

Expert Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include architecture development, RTL coding in Verilog, verification, and mentoring junior engineers.

report probem

[### Senior ASIC post-silicon validation engineer (m/f/d)](/clickout/afbf11743ce40ad7?ql=ql&sig=262bc80b57d17121fdaf10ab5e82ab09ea239b21&e=tRLI2wcHA5YxRuhv4DBnVcl2QQ2KvD8a6BvfXxqZxtpBfCtXsTTElmzGEf6jsdQ7BX_ZLsPx6fVk7HqjfVrUYFg0P-yWr700oIUfyXuK41i2rZ9am-6rFTHxsG5N52sJk8awAOo79FUo0KDon0mxB52oZi79I0VoUbpb1ExB7OK1Py2cUvlsC10jEMecoz70NX5YVVf1Q-sMSB2pPv2cAbCpejLMwocxFlUFIPeAwFeJpreLNMNQCwQ5w_kglf6Bg4EtSBqx1cH4PMGviEz06tV8rUQ5sj7CoeogFybLru14mSHDDivtA55BATFd6EkQNHEZfrCASqi6aUsd0e-4fhBhNH5B2LceuqxbV4rwsPGbEQaQjADO3ppb7z8ZzsX3keNLrcijGezdjShQc-6JV1SaRr6-gCChc25SU_2MRndIQ6qDHONQuBkT7BdixGLIH1nqfFynRfz4EojD23B9P_w5-AVvWYwRtkkaUonFO3RAr--3sDZ352F_h3KV71fqkrNjIGKuDUXwURgS5M4D4v8zS_ard3VwttW0fDiG6Kgf22FimaSjN3YDEAILiwKVA42Z4FyQXNfEoDJifqG2JTJ_JFtErcWVs2XzQrqpm9_Hoq7oIpFJJEIMcGHfEtmL_FQ3XLqPF5bjG7PKmxyD5yzszUX-0U7rbFi-Jw512421dEFz_NOx8cf9PcS-qIfL8Ayt4mSNgEUVwYcGnFKka7pbEg8iCZygNvKMw8-zpWiLk7Q3u7r91GkF7Gf-ccpv7TvGUJXbVpNMNXLQRH5Q45PsN36d8ySprHR8FW4UDEi5gUo7fDOVcz_FAH9t0zsBbf7GeZjaVPGMT20tqSUDCrI4bceLUpg-gSQQKhVh8-1aczP06cm6sO6aavWzMs3aM6KeHWgnQDL-6W2ZW-pheZHjArLgRAUrXkWr-73YoAgOGWPplGOPLb9-s5Av962RiUWj7qJCsS1xCSX6UrLQ_VT0P3msQbEu9abjwsA-W6pcVaCMhKlJ2kGpPOohfZGSRI-TzGcrgN3sPZFjr4oSOTuXmduMMNCEmiaGq6vK2jc8U8UHv6_7YmI-7zNhC-gwcmOGp-v0HOr3ZoQuhalJ0HfEez6BEi1od0ZsrX62h8xSzKc4DPete-3zXyz6YLV9GnIb11gz712DC5DfrVgp0v2a7GwuoeKNR4mP5aFBaNo9OyGeDecoC_8nEKHLgELKzJE_vFE-Dm4UxIfmRA4USfIyAA1oCVXB433XjwsqJa02fPLUGc3rDeC_hm7bSrTCEwsd18NWtbihn9z_VzmTrzUz0ZfD-OQ3BpU1iIhf7dF1Sr7cSFU4RKlfdpClMyxYG8Jk05q_K8NODxVw6Dz9BJYlG7aEVUUJGERLqT0IIz7-qy7oYkEzewtGs4HXhPR1xAcO8zeCMegHlGBtTnpZa94UDx35HY5HGiDOaEvPkor-jUd2_ADO_TIf3VVu_o40Vzg&prev=RQ7CA2EADCBEC2D8&p=12&pg=17)

* Advantest Europe GmbH
* Ehningen
* October 8

Senior ASIC Post-Silicon Validation Engineer develops and aligns test plans for ASICs across analog, RF, power, and high-speed digital. Requires BS in Electrical Engineering/Physics/CS with 5+ years of semiconductor test experience.

report probem

[### Senior ASIC post-silicon validation engineer (m/f/d)](/clickout/ac65f05e9a69fc59?ql=ql&sig=c8e12befdb1ac5e6a58cafcede331dc6c153316c&e=e9R3eofj335q9rlpanu8VjrMaSDd_vR9QNrYvVGACbLMMFKEJHTW_Z90TuPnG0Ufv3xadRVQzb-s9YaqJZUfvVgaOhffSFG-Nk7Cg-9XwiJVtY5ZRLd6Blz89a0Aw1qt9h2VcEvLA9re386j8Iis1E4ixMDRmA88BqgxSigvdtmv_MmeKoMbbRuAlE6HbvMN9ZsDu82I8xGJ5e_bRA5fF4TNFVaXOZVe8T5EL3yRthHaDIXr0tnsbWNsrMlx9gTpOsHQGQ10Cg5tfobYtobt8wwEqPjRnDGmVuzx5OvZNMx2Wf7vVAehIYU_oosA7YmjvkYVlqyzHDvlCr4QuTOSjxINiokBHRbGte4cHBrpA0_CxOkMKS4yBVzrq8d8dk84a6sfmsBWA-O-3YBlluEFF45faBtVIybV2p0YjpujmbFOT0ZZKef4uYv7zLJFF2OntGiX4ezUBcnXkmxH7DF51RDgfYsLzzvn707oAGqyq75-RQ41nt2PaUyzg_J6W996TtsCNA-tuPQ3RM0lUi0BvgfiU_s1CXu7e3TThPS7nsgmAReu9c2ywsMFaZNEYo_mIxYFSEL7PXP_CUmYZSirSVcuVyXiWOCFseym1PwFvBbyvVzYXaLttOJO6SN5II-LW_C9LuPwW-sl58t_sckgHFn9KffK1wSr3Vd9KDzPx5m7EJLlrWcsS_FzdWSQBgTu5o2Xl4bomn83_1MAY7Fw7BiWIFTqWfWYi35uonMkvZpO9_i6Dy0dNLMgrPg0OQ-JZgtENoLllSrr-fFN6T1VbrEcv1chxx0EfBXockkyAknISkgmvNEnAeaTDbY8LiWGXMge83M4LQGXjz443T123DDk346zJ4T4HuRz0X91rqakVOxb3TPJ288iYGY4dGgSHnELK9wxc5H0SlElKrAmg6892h6bmbht278b3-txqmbZ9mapgduYw5ixW5pSQ8k4_vn-H0HDmg9ItSQnqSf9uFLsdcyJesr9ljZ7fMNEiG84178nqLh-XybEEIV4oASrOk6Hm2gWsSeLmesWxOH_C1ZxPU1Oc_fR1wb73dIGKgpw8Qa6QIomihFX0KrG45-HDrm9zO5Ew8E02gusRIBw4R1g2S0HaBvQltrCCUnZ6VgyZnmierTBK-7OeGI5bS3Yp13fAPQkjRaFpzf-BcDAViE4HB8PU8R693MGejeVZY5omjgD8KDibqeVd1-CUntwPtijS3qwnslLiSNGfH64wouYTYfGEsFEtY3xt2sl_h4QJixsz2MMYb8K9yyuK5lBFoyYWj8_dD08nwlRNT04szgL7hzivuPCCl-mPnxc0N2iX44e8EMhe8Y_a9rbPEvnBIQWQh1fftPiMP7uZEjNL1LIaSrj4QPPNz35MavY8TvZA_gJxOa5louwObp_AmKaxM5aDOenJ13OktM5oc_T8AwcDhBqJccpROC7PSw9e3s9b5U6whAa44aYEj41p_MOQX2-IMQ2&prev=RQ7CA2EADCBEC2D8&p=13&pg=17)

* Advantest Europe GmbH
* Sindelfingen
* October 8

Senior ASIC Post-Silicon Validation Engineer develops and aligns test plans for ASICs across analog, RF, power, and high-speed digital. Requires BS in Electrical Engineering/Physics/CS with 5+ years of semiconductor test experience.

report probem

[### Digital ASIC Design Engineer (m/f/d)](/clickout/9b664bf867f0d5a7?ql=ql&sig=7630d4b4c9d16fb24d7f9c91a69b361f89d06a51&e=QTZElSZFpjaxvnTZVkQ6fxvCXXnXeBiabZLjEW1r_6Klp95VZF4xDDI8f0P_z6Ez_UOHhjXQLdR3wt-328yxksR15jN9GYaQS59Rzp5ornuxpVwTHA6Hvx2uHTZ1ZHnB0iBXHErtBvKp83T3L0oLESUdzajbzpDY5qnY3UsBQlf6414gTsmxnNFhIcnLxdV_1lPbUopyepEGkeIgQ4bODbgx6Z7XZwWvObhCaQvQ7BNIl54VDc8FgeqY6NXQal2rzTljYrAP-HkH-ujGfiHAyD_PQsDupWUmn4BQjsBcKkvtKwYCnyD5oHwk5RLvdKUs_idTbi1pKr-HmBOB_tOhJ77sBCXiZcbLxwSEsp--9oKdJS0yQ3gKDFXgQysVdwky6LTSPtBwpA-s4JN0FTw6c__AL-xsUPKq1jAMLzf3Os3pipt1_XzOBRQx6fp3KjPZQjzAo61iS3BPR4tRT-GzModmTUOyjgxtDS7B0y9ziMAVCepeSPnwEQvQRgtwNYMq3X05XxiW3w9wNJQ69IBDFZcY_F0ZUmgY6MuTiYsSrsQcsPKoF2DsXAPVnBDjTYq7WJMTDp0xc9mOUPdai5WcxLkEzKWdM2pvdIhGnVHFRS0iIxiqpplwPIwIiufkJq_jhdS67Bt5C-6xAks_AguNTUerEwr1w_hO9SzlqoZoNmJrfgewuQrB6nj3AT73TtWIostzegVgHnIuttRdPtGHNs9EebyD5uBptUBxtL6QfzXY8HpkImpso6PRvxRWmBC55GjzjKmex42vKxYIrfNXK_Az9gE6M4ySeJGUun_-c-EP4_X-FIRzsJYmbXJRWM9pEqRWnX-EO8fNMQLI0Rhy1RDZazNVyJtmbD3Sz-FBZTMAot8SHA2zlmMT8ZC7Y3o8pbypDDJTqTxArO9cCNBTF7JIZ3p64qSkERrqR-c7THdYUITsSuWwyh5PB0iMZBEdRjq8SP42MVG9A9EGTtO5hjlIYT_qlTN21Z1AHJd7wF2-t4BBojPEu-kJ706dR_FgoAzNrqYxAx3r44ldub2hEfVaq60NOBGP7oCxsfhQk3UoE6HgpqLr1XpLeWGLtQpDpfaYs-Rd38jt4a6M5epES_mmvKJzejugQL-vtsNdDEaKMP2fK1i6VZ0jxgRPvZJ4tZ18xeTPwLyTCAtxQJHbCTJJt3BJDIGtfZkL7Y0YxEVa8HKkvTNZuSdCCSLh_akHIG0UYiZmoXWNi55d71yHFeoTWnj55vl1nx-3j8CYimE2v5-2dukYkBlhiLDYXuzuhLlYgImNlhSeIifZOCuzv2HFbRtwlpanSYiNOcqFDn176tVggnW_JD9ldnkcbjZga5I-ZWsAIvg1Vx484RSBhLVuy_bExq4hZNJg-k3x1g-CbtEPUj6f-aIjmZ6X6yTvZvB3YIJeFNpJteqli6VBPXLOnWMlmZw4lJP83-MSMx1E3U_ekds&prev=RQ7CA2EADCBEC2D8&p=14&pg=17)

* Advantest Europe GmbH
* Sindelfingen
* October 8

Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include RTL coding (Verilog), verification, and end-to-end ownership of digital modules. Requires EE background and digital design experience.

report probem

[### Senior Digital ASIC Design Engineer Synthesis (m/f/d)](/clickout/56d3cf3881834769?ql=ql&sig=c24cd0676339809dd66d90876170aa58b80ee29d&e=gBjUIfIfKdBdz_Yty3r426_JsHK_2t4cPWnllWHL6x7frSf4qtO-HSvXc01wFIadIcjThLQodqp6tP66u_w5aImavY0CWxVmjpCfx5wac9qx_Z54r0-V9lHe7Tzx5q88EjEXw2lYTFftaod2QN2Z2f4Ghop2aotU0BmJf1ejmf_ZdpvUaPfpvQtGg-fWWfX7I_VIM2h64iacLYUB-N-6pBtOY8G0TTve6uxPCqmMhArX-p7t_H-KaIgIXVOok6QnI3-InWQizoNHYr8AyMOtxnOQm2g_Xw1p5J-HLa7b0Ms6hlyE3Y-2OpCeUXK7vm6xxTDJzmjW7iwYAJMVaH2gZRSGfAVB75UI70aclfD-xKSNXImT1iWSLrufwSVWSEP4XXcmKx3_jcthCKTH1-tLNc38tPrM4m35ICJhSASbU8kOQN6JRjJRhcGrAm7uCTORy8vwi2dVy8Ix5Z4Cr23p7hsTi9RjfJYQuUyVDwsYec0PATUSCIPjNDO1hXJ2I-WssrWKDa-07pn9sGjZvzoBghhiXydiybQUkkZE9gEE-_Nd8mYsyEFt3CXQixEQTwU4q0Q-Aulx6BZUQ4PRdvU_iXQo3RjTLCF8E2DaQ_CiZETBDh8GTOfg7Pd7eWGjJhXtT86lPyFCSEjYMmiA0gvnI4rszqFtM00l5RTfE6noc-hjjvvvAK7O4Vk7XjGL6Vsc5wqnqTJvmfaA3qobpneautV4JXr1e76_SDsIAx81jhviOX0ZtKrwy_FUWaL8ADey14qQ9dXo0dIVF7JqEvlPruQntou6P9gxq8xUHYMgfneoggzGoWJAz-GubVYqrKZax3IUBzRZkzRnnZqxvTURZopcdQyJJdyb7UaLy7a5B3NiFQez0evoi5HFMbaUAHp2QQfHy19HG9MOxFag1p-ePwUz3rt-ijHXncrETW9-ZL_ofsHZDkkp6XtWn-XJV8thGgDvoMsAihSgf_1_djZ3O3V5FWplgUYH8JIyCF4yADbSnhXSwRP-re5MwJOPP-iABgN3TReGy9tjN0xRcpcHhiXjw6aw9Otiijfmlx8pMp90JCogqlLF2tUuAc5iqg7xYbfBeGfjhI8b54zIL2TIPZyyqaaBfGltxD-6Q7IJ4FUeXHW5B5VDTgFPAnBDqm4KHofwrALRGOU4dQyAAyLkiOxtO_3OM9Kfte6XCF3UAF7HzWLYfGgXFw7iCXv6zUTk08M4k0ujYs6cakHIa3kKmjxJ7dmO-HY_T5hpLZpNzZp56oxJb8PA6NQOrAijKRjmdkyu1rhdHyY2mHaqjE-kglaqf3_Sesx5Z9cwedLZswXZF0a8aqO5J6__U8DI6nD1zHizC-2p6z97YViaxTJ-c1UDuX4RKYr909jjRQCVwA2v6XAoXWzQ4b2zaz35OW-D5HNa8JdGguZ1elIMLkI_HrmILm9fDm_BhZkz_bzrWaFa3Sz8_mi_fv8JnjhAG11F_W1AAG3fGA&prev=RQ7CA2EADCBEC2D8&p=15&pg=17)

* Advantest Europe GmbH
* Sindelfingen
* October 8
* part-time

Senior Digital ASIC Design Engineer Synthesis role involves creating next-gen semiconductor testing ICs. Responsibilities include RTL coding, constraint generation, synthesis, and analyzing timing/power for complex mixed-signal ASICs.

report probem

[### Supply and Inventory Planner (m/f/d)](/clickout/92a432dcff50699c?ql=ql&sig=0e386c637fa97a7a1403eab97668943ef279a1a5&e=Xb0CG8dF2k9XeL9aV1YXYWsSAQ6aPTfXonTwG0SsjVxNeCAl-hBQ8L1Ryti__9ngw1-KkIST3fc9rX0HN9BpMOqTMmP2p_srDcVJC9KRr9gnnCoDOURuY-8r2BAUWaSzdNLPW4jRvj6utaxH6B1nHDB9mWyobpV-p8TdddeYFDy_EgPGJOvav6sdzVk1DSCe4G-A73MxslTAyGUaG_8QQYSn_2HujsgQyMi6MInLmW9eeQ56PjUc6OmoKpFOax2G_KS_x_061oKaNtuhoIyTuL7RMzpi_Lmqqs3E1eUZOKMz70U8MM4oXJCl4_g9I7jID94I_yMUlX8vrgtI1hjadqNQQI8y7xk8AnS2du3B8-F41WrYdpUqb-4higV6Eax7TLE88lqqvw61M7Yl4Xla1p-Vf-YBHVse1WHlaFVG1_0s4xwSuj7fXFqPbmgcUOixx0ptkLUSxmTq69BtxSpQ-YG6rTjqHkMy0e0rQC7IzKdMpEFi-6BOO3g-XF5Rk0zH58-mcv25g3d4RPxPIH-hYlPzck0wUd_gKyBJF2Lh9lMDB6NQOgeBGJcAOxPEXyO03sbl9yu4Zdf5yU7M12fgfo5hK8IwA6NHPw8ffQe6R6DaMzT-fm5WDkBgNIvF6Wcb5yShSbEg5Ow_XnSMTUjEZcEVAJV3ye8f2gRtGKnb2wuFeG92V6a54MxnCKAIxJWt-gyyfAXQBZWrhAcdbVULFy7G41Zc5xGGZhjfNLquXS9fpxVcsUsGpXGgCNIUpgrbx2vHL-ZyTrv6M4DzAEtoqrAMeY94BdebP1QYV-hvIBVSIqahjrSrl_qebyxYU_xA3m3kntst_qjzP6Leye7I5e7bP9RRonjH5ofSmkeSxK_kEL4s3r6CvAvRZ6vuAVCdVEh8HVkj5bkJuOyMOu4dStun_iT85-6lLbWMWFQekJKnKr4yTPDiTK_lkS9cIVXDdA28dCHYzKuS6Gva-VyBUn4G3o4Wrhk-WwmOAi8cFDeMbLP6UFtdqAC63HK_me34Xy3buRbmYKZYqNdh6fMuckd0yezvMu211Xo-KLhmyAjGkIb9TpFw9Id_5UJLvLAv10MENWOKXD3tKIJlPXaLCTPagbbo5qnL43cZjtzy-K7444qefdpbJKBaPIXjxn4Qy4PtJjzhKhiHxQy_XzQwC4s34YvI2T6sRPYAJLg89uWAu-lAYfhyu7Kog-B8AihtVtlDmZa0_IaoZYc53pJ_mOLtczwjMkVoP-Fqc2hD8TM80OA3LrPGBSE0HeXhFsI4KF4rG5YlN92AE0RUIBQKFIkq3J-mDcqkdJcIx78m4aLJlCAJqWOAlBxcIw2YVwDM13TPRTRjoygzEfA4kUt1o-g5eD9qbhOnoo2dn8iXBSh_ADJi4GuxnVmC-BemE-tz0pebQW0_VtWrry6bR63rlEqDTb7BqRROn5BPlvGbb2yHQyi4IGtgGQ&prev=RQ7CA2EADCBEC2D8&p=16&pg=17)

* Advantest Europe GmbH
* Böblingen
* October 8

This role balances supply, inventory, capacity, and risk in external manufacturing. The planner translates demand into feasible supply plans, manages inventory targets, and supports S&OP through data-driven decision-making.

report probem

[### Service Sales Manager (m/f/d)](/clickout/c74cbedb75b8d7ed?ql=ql&sig=0fe19639875d0d160ae42db0c3081a82cc1486b8&e=_qYcrTBOjf6bd6m0OgaP0FWqU7mLH5fSLn-_zPVLkpHYvgeCc0YgONAKsZ1xMUz0x1BHTnLrIg1A5WJGmkZ-C4EjL9XuSaUFOJrV6msDgT3pB5ho3HixIwdrXwdhmvKVglQd3yy_NJJREVC7PH0NZEulsNDzEy6hhXhBI5mjHZVTo2kF6CXQdG7nsKX5IFkKjV3G_snPWs501hrCSRY46y63oTGvx8tHi-sMC5o_79zfV7WGh3rxyjG4F4mvIQS5yb1Pp3sjmIH5MCJw5zXYeMucsOv3SvlSQU4DSHTAWX-J5V4dJudIpodBL33k-rNRK2p1rSsBUE7F7MfwUObmElxHdPOG3EWAv6dBmprjRWoyeM3ZnGjG4p_Me0xqp4_DwPSDI3FhGKPbR01JaffWuLr0OqatPHz80F5HpHA1ZFZcu2m2kscz3Si9BcAm8soVhog1QSC1Q04BzBEr3eybBt7mkNwHS0V2VRzRFbE5uuVTFZukg7ueNkwL8fJN2AtJii5Kj6huTcg_yb8XAQAHMmXCcpk9RSL3j5tqEG6OY1vJ4mJ7mWbsUi_2NT9oRoHWnJoW13rZqpiKd5S053ur-Va3lOaoS7k7e0H-C1yUVlpglFvpcJFYSxn6XpJZEWYJrS4LAxy_KPqjzKp-ylOzj_KbEEosZ7o-ms5nfC6uke90BQhtiJ8rCKGWBm65FG5e7wdbJDLoU6SFPJ3KFCjN5ntVlcRgTTCjSp_1H1futZ_bE8XGfklg3FLvRFOuRqkRuI1NREnDn-Ch3CcXobXm5AGPp61tYrAmbbRf0QP2fJHz56uK2zRCs1UDnq9jUiNDbUh2Bjw0T2nyCfPct6Ei2IgOz6Ej8tYAlBOHTcZSYNBHUH_N3UqbB1HAdVc7BdSEKj4y1BmrHtHkLY3Nr6FG0InJ7YIledwLTHu4eje0SQwqODnyrMGKX2OPecSXR9kuPpfF7vI5LFZSohIziDpPhd7AuuQ7LN2L76JVzbdjvTyABGVe5DdOdFNqdALz6xNS4XEVV2rWaTWkCLveoXfLaCVm4aT9EEAyqfCWvj4ehdm1Qx9WCVJ2fPgrPMcZaW5w2MnzL4-LthOg8XiQXHNe4onlSmjBJ92rerJFOzb4eijR_EFI2j-ZlLlH5ayVcia58xl8QBAUymo5WqQtwMEgHHQD5M6wg62-auI6nCmpFyzyRCDWXaaOfVo4RUK_0e0fh50hcukUv4uxVGi6tiRzfh6FISuGWRecO5jgCt2QSzNEnLTzoflLECsAIV8d9QQuN6YdQbeBxqZe-wLjGGpPE3odMEkeCr6T3yeno3bf96qfW6Ts6EWEb-lQOfVps1AC-PP-S0lZY4U0-P0rI4cf5SvyF82wzcMQ7Y0fb6NUaS5Ys-1ivsDusT_iAPDxHbBMoD_T5UfnP8HMGLTOu1hrpce0o7kTbDn2tKVzHPxmLAe3&prev=RQ7CA2EADCBEC2D8&p=17&pg=17)

* Advantest Europe GmbH
* Böblingen
* October 8
* no experience

Service Sales Manager drives sales of Customer Support Agreements and Production Value Services. This customer-facing role involves developing sales strategies, managing Quote to Cash, and building relationships with assigned accounts.

report probem

[### AI Platform Engineer (m/f/d)](/clickout/0deb1240b5044e67?ql=ql&sig=2242a6b9e682ce1fe1b13d8614c59ad06d2a2bfa&e=uBNT8Fje9Q7L3NemYKovv6hRSifMg9VCdgG6HTFoaylVVk-Ln7hHHMcA_dNokFPyaAwSXiX2_gCQ6--NaEzm42s8KPl--pKsPhRQQQpmjqeXsSLUSf9RnNh6ySD549Hn_EiKKweUe9hRNifeEyi49yreaLLcdSTij2k5iT-K7aUSAXZ4t8ur0lSpUDWQg-gUn6rfIbD1AzUDko243MqXSTZEwe9gvj0PyGM-eGOt4k84a-h3lrZlPwvdbFB5RNmhPLuQUZJmWF__xsxhYPSvDpIk1w3szVYTpgI2KUPbDHxlCRMACDcXKda-o0sEveHuUwB9tQAwZGor-PPwS4No-DCKcAeSI9-V53qb7oXciM75yJEqjBiLvQjse839d4a2zIa4HaKN5KMwSR2RCiwEdZWJ3KZKM3MVSVCtk-mdfo4TEXAmekE_c7I_luRCqDVFFIFSqMHkUxd85bSax0AB_3XnDler0g71hNpx3n18EyCQ7cqH0YM9g_xYA_kQDjD8xEp2KvZBWWMnbrguTGq8psPm23cP7a8YCWoewb70TJ0WL-uQ61Gq6u9G4pJkFScTt2J0E_U1_hMRztpjcdBj34XOBGIbSOdLtJHhMhuqOqkSo4AAvjIEUTq_q_HueSmrz4nE3EHodSMjcDzx5XrdbI9W6N6HJ0IZiBsJN3-hMXKgmYfOkDnqHyCrh0t8vVr49x9GCg4ccyv1mqd4QQ0yV-JXkOMSCpdC04oMvd5_yd-OsfUAabWhh0hDAWwDXUILl0lwkxHx0tlBUaHFoWByWkc5B8U-rD_KEkKx9WKFz5rzsBZPG9UQHvPGfJ1DiVFJMh3HSa_4OnHw7B1RcFn3V61aH5xaJVTaDk9i-akEv28qQkjvkdmddno47MrmRlW_96pOgdoymMbVmaA3E73zfxQPIMTWpakLX_8W0dCkIBi0-985Ga1UVawQOyOXaTuUxjzRT2ZInCZMicQRMpO4ZUyeJzWxdfAKq0gy_9YxoJCpWngC68cg9cFTNqhbJAw0S6vRmuiiXRYxylZXyfYZnF7bSTHYrxzuHf6o1LkWMQwWoIYqhhor5x0bQ2XfXGZrQ5OmBd42PBH_Ii5BBQ0zrUNjdA-T0Qk5pwmcehAwfALkq7KWgY7fD8JW6Qh3MWiFAnn4c6qkGD-CTN__fEYU3aJh9novPwxDWCGOwYyMaXaQn-GBHWnMOH5xH3iAh1rxlXiddgH15bgZl5EA_QimBdQxv8TfbXH8fvAGCipn5cqASJMHI531bCkDkGNHT9IWwKAJEB6qLIlqQ2QvBsTUIL-YxzWLxdWGQhOpTTzVEnOLbztpZPCRzIQNBM9RZqmEctbTd1h5b6pBo89x-UDw_YDxMTgX8RVhZfEBGURK8IoFu6GjCzPH0MUT148EqZgqGINCnSrrVuIH9SQ3qDMWvUGlUbOLW6XzZDtz-wY9Gl0&prev=RQ7CA2EADCBEC2D8&p=18&pg=17)

* Advantest Europe GmbH
* Böblingen
* October 8

Own the CIT AI platform's operating model, defining standards for LLM APIs, RAG, and MLOps. Set technical direction for engineering teams and partners, managing transition to production. Requires 7+ years in platform/ML engineering with strong Python, CI/CD, and cloud (Azure/AWS) experience.

report probem

[### MLOps Engineer (m/f/d)](/clickout/7462db86522d8489?ql=ql&sig=d6a9948b3c39b62e1dc52dededf6acfa027873a2&e=RtOnADndK4HH1Te7lojXcL4yjbLqaKAk6Qze8LL3yNd50JOItT6tWnOQWKWM9C2tZ_6JrJrCY9XR5iFkYUH5T5K9B-mAzrpgZktoioww41r5jDMaC5M7uyT2sT-q4uOuBNhDPJMPpOQhn9cf83NKiw71z4suBiWFyOg1K_Zvi4NZ-m453HchyQlWT8xeanBerG1LSlEXxICJ8nkhNDujgKOZjDMCZOSsnsRhaN3CFsUBZMzx0IO_ssYloDn-zUSv2x_wjAt_r4pyuf17w_YsMAXpOLAqk0QvL3V0mkP9N3H1fJF2bSwvs-tXbQKx59Ot6amIPytzw3hFHyRgPp7PdFhwPPHSNokweNRrjAwecC-pU99i8FukCze7wXUuDzuaAYptuXGIHzFyK9BPc2Hbod_eG8hEgQTA8_m8CNGtaNbqOesXlvxG1ZusFv4_fvdSHPkXbwu-28J0U-eoCkh6Fq_6ta3by5JjG-wyNmgPNioigTO_w-wW9cJ8uBLIAfjN5_ZzT0Lv5lGHA_MffCwCKXwAkSJosTYD1WGj6YRcWw1ZptEQLVaLD7_SK2ucNzr3uLeOVEPZmZkdFK3jCuPL30-i8H7njLFR161PSnZ-HApa7sXJt5UH6hrjXEnTZoYg2pMAPvB1jExsZt9Z3nAsQV1eN79BiBzbFzXNyt9_b6on466GbZwNji2jPwvGvjO9CfLA0cEDDH3eh73hJ-MYIMtJb-Oyu5vGhV2uk3Tnsdw8lavDqRoOCSsco5sWHBVdpY4hInAusvX2r-z5aN-Tf7PQfLcE3t80CZ-w36JxGLsZ2oQgwVDiaouZt1706U6OpAi7hBEFDPfbO8FcJNJNlubgV8TsOqrdMzkRw8cugcnxTCR1MxL3iWEHqpYLEAKMPYTpao9rxH9pgU59qPyw_SiXYmUSI_Vk6caimA7B8-NlmnprlQn87cfgBoroJaX7b2E0eoICMfzmfpeZSTqU2ZlZUxD_ujybULXOHJt8QKkQIMQz1GDC6J2Cc7D0YKSYxGYh_q1JE8A9JNLrhCxlwSjWD9NOV4u1VeOaHnMCvD3D2C1TCGJES8Luv2X6JdkD-ScBBsdlk2gUeMYWXwZFwvgv9900cth7myYl-0miHX6CnQlyt-HcGDhgsmMALqUcVmrQmJYcUx_FnKxwjGy-YMFCe_TsKn7kSd9GP2zNjJheYL0Ozl2ZTM-UbMXLcLnhSHy48u9p5Dlia2iUw7iw4D8lMbliojeoFP0KAgLvuYuPSKoASGh4Y9Bm9NGP7mJnE7JuOwYUsG1mPz2qJx9efT_-M8t6w2FL6q-cm3rQ7nputrRYQHkzl9tER5KdUsCffyfJsziMwYHsFJ-cxobLamOdm1Ox0sUhnvWU22duXF571C4Xs8fyTTq__aiRKT8eUHjoOf1cn_MW3ONKnn2wGuYioIdKqghqxA&prev=RQ7CA2EADCBEC2D8&p=19&pg=17)

* Advantest Europe GmbH
* Böblingen
* October 8

MLOps Engineer implements CI/CD pipelines and automated testing for AI/ML workloads. Responsibilities include building model registries, maintaining model serving, and configuring observability using tools like Prometheus and Grafana. Requires 3-5 years in DevOps or ML engineering with Python and cloud experience.

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[### R&D Software Engineer Maintenance Framework (m/f/d)](/clickout/cad8a5e6ae1d5e7e?ql=ql&sig=dbccf63e32ded19e1b7019bf119a1fc4c8fa4df4&e=hgsL3xvWhiggJquL7wEZWWe9gCRoJgv6sJFxLxFPEzSgRhX4jOOaA_SWm2gsSboVDT_tZGd8HfB2oVTnjkFnYI0aY4mUYJLyi8MtxL90ps4NqIH5JtjkCjMqf_ptls7Mki4AoexE6MB7lzFbIx-Z6Zrr0Zkfgc43N9FxjbSNgQ5Z1z_DWPJNA-84P2V8Lh4kJ29PjzUTmxSnaSvrr0uPwgl_p6ENiUzLHQX7qfZDa-bNdBn3ycjkBam5Y8OvHqC_nhcsk7tjnThz3wUKe4rL-w8fjOGGIGSajkGikAwfbIHmsghK2FZrFqUKwQDwXAioFj1WTnJeEfNKfCwpZ5wwuoWRM2kaHAFmDoFcq99IpK7PUFubaDduJwZBwk-NchB7IcVJH-CkYLZ_J7Ag9n3_oqUiyfKVQi4veZ_0vXRx-IRvQGy_4JTgu6BgCNzGl6--t6oWjfMDnBoygrSWieTC-d-3yOJk4vi-Oe_S35apM8WBciYxINDbZD0oKQ4MlskB7hr8MdGrffjTXLtJO3WJvUZenWHmJjC42RGsuTRe4-JPcdSdR91WuOeyG1Mdy8lsbRpbfCaNXywCIMx9zcoB69NYAT5ebqluEL1R6m3HTPrpreLXb41nWv0ziy4FvPvU4yK2Yrp_88ecLVBL3uphHou4luajA_R0qop4H_SX47hgi1B2VahyChP-W3BQdErsGbJ5HvbElvQFUQ-ZLx0HQzfLjskyNTbq8zkc_OlJzPBD5NlETVd2PdCJh-gbhTcvNPiDn0olwbE6AXUAIltzVw1rj_PXMXdafEpV1l5s-zbTVnhJyYIooUjLBrcH9OT7C-iFngnNjCdXbSITVs-5KWpM67T-_qiL46clmDv8FIB-v4bcweO9AGdDghVukGaIhqXCpCvLG-NQUTyylpbStYmeDJuts0GLCGfFFv-8Xkg4zFnN703XqlHuaoxtFkM0unUobH3k6XblWQf7q4jbvSMIHgvTQQQw56MXnSyUDuDSfJkvcLN1ybCuLjYT0yIkE-0PqLeiPKvjxY6eiOO9OBS8siQq8PJaS4-MSA0fve6Pe1ljjxgkpGrXu0kzV0Plh1nr6T7ND2pMtAvz16SZIVxZNgVQA_RHRUviYTZ3rE-DLsNlYr22eXLNUrnXgvvL2_AijMQNdvkgNyMy8MYPk6cC4X07WxrEhkTVumbQNkxk-XqXAgqo4mAiFIsXn-IAL97Z15UStrQooDCP_kkK-FLV354ophbq5Y0r-KuX59BR9bCKso5lmRBNIdvCSSVAknZxcaQG8P2wWXDOSAGPBCr1Icg0ykzYdOs7kOQhWEffwfWWPG_a47_PZEPCAbZ16jSs8xJoPdA91TjPvsCiNjgdkR0G5-FOilzCjTdSaSgTQvNRigUfsKGKDy02Ucpb-ixr5xtvtwmltZ4N9R0Ncoy_vPphoK5o75Y1TFKSXuST9iPeoLBIUd5MqlsMIo1V0x7cy0mcQbI&prev=RQ7CA2EADCBEC2D8&p=20&pg=17)

* Advantest Europe GmbH
* Böblingen
* October 8

R&D Software Engineer to design and implement software for the Advantest IC Tester Platform Maintenance Framework. Develop in C++ on Linux, collaborating with stakeholders to solve complex technology problems within an agile team.

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