[![English Jobs Logo](/public/img/logo100.png "English Jobs Logo") ### ENGLISH JOBS GERMANY](/) [information](/info) [post a job](/publish-job) search # 3836 germany English-speaking jobs in Germany Include languages [+]sorted by: relevance · [newest](/jobs/germany?sort=date) ### Note Some links might not work from outside the European Union. Dismiss [### Private English tutor](/clickout/24992831de77a71f?ql=q&sig=ac60a11442d8053f407f039850d94cf29e1d9b13&e=yQtImoAvskF4FWbXVgP7zSiatSjwy0ijIc9ku8P0bzBhdEndx81EF0zLKORGF-FcBFwYd4flUfXOPPJr2PbWKy2xVXW1LBW6SlS4GLpEQ0X-R4S0Nk40WGHoMvHJh6046SB2LwfSvlc52Qtdd0eTfdrYa5xxeLS-0zdmHvKBlIVDNuwMC6dJt39cuuVzcrhLPdB-micu6GU8_3dgtF9DpHXd6I_FB8iPTRd6D9stF2vR5EofhpQPT6aFPQyM7XPojZO6RtDDLXgN-l2-ED7CNgIvKUAiwXrQiFy3i8_E0O_hJfQNqYiGyY9X2ZL1ojvivIP6726617wMzjdjnpVbaML-I1EZ1edhHySGkC51j4LB9dTCFcEQ2OR0SSlSe5wa33-tpBYTap0ceiDkATLz-rg6u2-TAYJMwK5ao0Ds4VvVbHc-Ha8ORW0OoLDSaMJ8p8Su03wKNnD9t3iSTRHe6zyzoK3AKmxeG4boVTll1iccmdNBOXp-JX3tBx-i5YRUSpJvjZiZztd5YcIIYqgp8wSkXiOkJInYKkTqmoJQJP1X64DHyYdH_HA0a4-D2NMt3ZjaO8ZJxfXUhCPKYD_efz3nUygE-X8SIRlb3xaFWJBaQEd60n74NXNuUVu5uJXFHaJQjRMwhE4k0N7bGZJw6YF5Uo0RtmW6Em51QqeMVef1HwfuaDjVSiJd_gfH-XX9LrjUO_oM3fwjqkVnOjBwb58tkMxW3MB-h4qDAx03D6SGRkv0ZisHsPf61FDwI6r3RFv0lnYjUZqEjXLcXVr9iX6I7J1OMhB1F6FCb1Qgs3G9DsCJwQysMn6QdXvJz-Eri9Q9O3nC8p1EX9zEj8aVs8X9IDnOVj1gpUvhf7b0xKwObKlOeIO96kcmnGRhw_aFPLSTG5tW-oI8tAKevSUvAqnciwWV4sxXVZJxO8DYKY9gVxc0b_yHErEX6x7RIuPL9C-7K92_zhtXGrmtdQ5FIlawMAhvDdf6nJjfEF5MgwWVfUfVLKlPxKvYT5-FoYXJi7-BcketqsigaWFiHcGYJShW4qagA2C8zVeHxJI3oBGkBwZGHmuQ0bL4_xgRsuLonuAwaaumkzzObxfl1NunRi0CWMYp4TEtzGuo21fW3R20G3zfLL35WAjI51VIpSfzAt_wYdAUfVCvNe9rIUwA9o9tldxAZosfsokrCe-bR4HHDvb4tXGhjgL2NdofQrimokCNM1Y8TSXIphuDU7llGsk97nGsUToDlt7OTdRn_SoHl4viM3dZmVaK0-WxLp2VSaLIlhr8TDTectViHdONkNzNbJ_Ak_tFpFUsJXeG7_BIJXuKL2LXwbFhuSOSm4MC8u9wSXyKhTBb7wOABROf0y2m0FHY-YAc8ji2BBo2-KKZXkQXApMG_xCj5ukx3kKs0vW8x-28lgxF7eLFXnizFK7xz3nzj4oeJPBnQGy3InIXjZEQGg_x8Fw6KMvwHs8OCCBYahxb7EQugGsnHyoPfU85fYMwPetOzowyJ4rkCHCXVpbH3d2JevtQllTO4tBDRBwbm9V4OmZNsRfIlozeErERDnAYhto7iITw3daaFuTpB_Bqe380hToaHtor2Sd8vlG3SoYqoMTpdEbfnI_G-TQOOJY3mzflY0mf2tWW88l_1gok5K4dGS5y4aCkSV1z5dSeY8J5qqxCUM2mQdF1OIlnP1RNppJE43NdxspcRpeFlkNI9LRGdHOkL567luT_DqM0_b7f1ATCCrmqnXMumwtR_FmTzC7aDeLU4RTSXZ5P031NXEe_ZU_E7YKI8fAJtjtWPFXtMbR9oY-152u0q6fcdZQhfEiFrgcINci25oA9wwj5riSIFTSyyXS8W4Q56_io7K3spGxwgq73r3bdTzDfbSIc68Defp1FUNQUgNpgwkt2lV8QSjZ1IP1F233GdvQjqq6IR9rlfCt5lE0ChQjpiBJQdNA-xNQ1VPCchH168dLD9H6i_zMJLimTckOrZT99Z5DZTbKfAET_c7TKeZoeZpXEjBimbdrPDTKyJgCTQYEQ31FtAwUuSPYrQcw-Gw&prev=RQCB9E4C1BBCD8A7&p=1&pg=182) * Nachhilfeunterricht * Karlsruhe * October 8 * remote work * no experience Motivated English teachers are sought to support students remotely. Good English knowledge and a pleasure in teaching are required. No prior teaching experience is necessary. report probem [### Supply and Inventory Planner (m/f/d)](/clickout/8a7a0de2e41081d5?ql=q&sig=0e386c637fa97a7a1403eab97668943ef279a1a5&e=AwC8AjpYWVl8hj_DLch0Mxvh19PIx84zC7RbsnnrrVlzoIL-08Nwam40uL_SB_sgRYwUzThjeZFUpYX8DdtsYb-eo4FZHPAh5KOzY9ntWlZqH9Q39HU-kMiypckToSE-eT-FvkNQI3pkVKJYsa6lN9xJN7AESrp-KCn01qa3fFVfvi5Z5JOKhOaWbYUnFqrUTIy_yKx-PPzCg_Sth-ymrSOajOHxqNot5WtpTR7Xhc-Jnmc-oO9LSzpPQhwfn0ThgVKHYxfewDyoJ9-0dAflCTJR_S0EB07tfo4t2g79cqFEvGESAdrS0EMT257wEZghgZi0VyU7lj1Yszy6FowvfTlItBGtcAkCBh1FIP6n6JSBP023T_isq_69UGAX_bKsSvhuFSpt348-Ib7gMQpMSXT3J5hqj0FTqFK--i5Nd2fPdcmSJ7JgVit8PEYAWb39ctOr4-g5_cPqbgd1abXKmA8F2NQHty6xEHnnC3S7Ar5qf4OP30s9AvM61e77flcvaPMXJaUclo29Alw9aAIQlKxXAyH5O78Y-vdjGqtD03nR-wbbvtSxOEZhPEryCVNJWqOuhBz1MxDzEqbMiCMYf1JyF6dNIpeHgg-CPtd-Fi8Ktb5l3SgWWNSMiMUuLQfg1-_l8oL1Z_e9g7pSPwNM0KUSq7_6lcZ2VMz_YiJ0QHzmYSwYanFwD66JDbOlHvOjmBB7sVssaeJFXiaL0IoNUOTlm6CRnviaThLm-Wf39qZpKNDEsoM5uMqapoPIVNpIE_dzxlsO6xWbrCqmJkRc-wz9rBKc4K-8lEGFNvZLLq619vl-3sbvV0l53WBsoXBYzlMdl0bI6pTpARo8uG4Xp9O9g7Ma2MJWk1sWPeQ_74aXJc2QLs1Cp_oxrVg1EdclRBN_e-uSPeKnYYYR-ywH6O6KaZGPiM7P1PGdXrRwR8Kw91IRU6XSb8rrviEZJn2uj_DKclqp65FRgCIOhI1xrznB2oL9r8DM6ZMuLaXCCKnJURn8ACHZ_ER83WHXhLr1YhpIZY6ZC0kRg1fMY5GXRbPUmzoLky3Lw3IDYzNLhEvFm_xpodQ0HkJNivAG_QQcNbzVLCQbEQiE60aXOcu5hK2NiWULuSRUQg0s4cxxW_SBmOZHTuUJqd7FBuJAvhkgJ7xI9yme3TO-7FVcFVGS8-sH-AZSkeQs1qm19RfpEezPfKGwhAMw4LASgDgThGW2CV33qMO63e-cWV53d8cR-g_uuF0Sxha5hWQAfHiPfQCrOuSOfuIUeThsxkbGefNPHfmw58N2gJZPMtmz3PgUGMB3n9x4VUWT7UAEjySBREmMlLKvsxXU6J0vGz9Z4kx8lfR6htkN_fkj39_OevBCODViDTIJqzMdfomzfB-JoKEOrYqa4F0t_ICZKVHYJI3ZRW9YF6zDWVJFNJ5noLu15YkZLmSOnN4lQ5-OjQZVQ_-KcjAZAMIpnA&prev=RQCB9E4C1BBCD8A7&p=2&pg=182) * Advantest Europe GmbH * Böblingen * October 8 This role balances supply, inventory, capacity, and risk in external manufacturing. The planner translates demand into feasible supply plans, manages inventory targets, and supports S&OP through data-driven decision-making. report probem [### Senior Digital ASIC Design Engineer Synthesis (m/f/d)](/clickout/04d81c2684a65c35?ql=q&sig=791453d78a8b342e667363932c062051265b85a5&e=k8yfaguYGhGnHGK6o9WT5HZ3eaqL-hMQH3d5iFlvT7uYAU6GnxHdwlUTKLAQnr_ZteVOKo9WVyFPVNwrn0TOctqTpyF_oHICfSD-GCqyjPUGmTyuroJnJt6GS1bPXnzyJIF48jGYSZzbDtiOF_5vr19bN8CjO1f-ONLyhDSCeFhvCwUuDlUHAcg5T7z5OUjz7nE0ZzegWvpFXdCcw0HdFyciYBJEvp79SDVbR5dL9pTCkw9n9ZlPUMkVVJY8ud_ykMTOjIb5RXirIsLnOWs_V-eLmrdt__6dysgA2EDJQ5jvvt4SVjqIyfeo9WfzWTP6Bc4_USeEXogkbJ5C9QbBSRqHHOHK6uFrIFXOD5WCksXqwpXvL4cJWCDjlT-b09q5LYeg-urv0AG5C3sduWYBSezmb9JTSW0Q9Ig6hNg-mc9uRdguQyMKC8x11_NVfnEPFNhiG_iLAUlTJaVf2fsTavDcYV5swNYAze1rwJdCPv4WMI-T46zWgmCdytktTtxYfz8MH-FCeJH17d5Su_TiMn6TNqhnsRuaHUJ2vQmidACe-cqC6OYyVqFUpj7PY-DLgAqwbJwiLefATvWarZ5CA1oRof87IACYdQ0VPzZJotw8hzciJ7gm8DLjTEahf5jYbm-XKXowBrOlEponEzapFfQquAlq_Q4-F-TyRa1gh0cMSbTtU-Hb7ZEwHhJK_nnlPkbQ1AIltmA1cNgk18xIfmd289TFH9ySGHbRQgdbhI0LbVUQLPO6tWwCGdjdVNrlUikPnMI7o4KlXqy2kwE2Jagj4AbMXddemQP5P8Oh511Su1sHItWZCrIUY5vyxbZKJlMTQYM-FP2WocDh6XaMd-hQUVsrlnrXv5onPda6KSlUB28o7pg_l42q3TeEMjStvasSKn45cYuA-vciSQJYnjjbUOe3uVBQd25SITKhygqy_dj90haAjJb1Uwz37z16UCU4lnatYYo13MuZwNdgHU77tqQicYEEIXFGaoLXGYQO5xEYjM8B5ZL0Gkeo51uvvBmjGVC7Eb5I4tREkamAh3799Ath2oXUBMlx_0UbrgxR6WBa273JErurVGc66LgXBhHSrgha4ryn3kRsDJ0HP5L3Rn4tHKSFOdLFQio5f-BAaghC7LOLmXwJ2QjDInacjdFX5KeLcUbIsoredwd-j7zTSRB4x0SCQDiV2vXePO743RhGGVfSHyXGLItTEA-1aCrLyO82GXjmkMXvUB7_DhGDB0melXV8i2obBobxY7Ywy9D0H86mGCynglWN9qnvQYFuXIYI8UxKHFm2Qoaowl7rzVB3EEMOqlaa9oLig9sETD_Rhpe_Wj5Fk5pgN34WhKmhVNKRaEgznioQ7SP7ONJG6pdAgz0MqKMbhILVi52YngrIgFfBlnv1QFyzeO0XJxkae8ANM1OOeduzU9LTLNAm7XT3HVyNJ0jZPjNq2kQ59ac3eFiY6Q2yn4qMdi-OvGTP&prev=RQCB9E4C1BBCD8A7&p=3&pg=182) * Advantest Europe GmbH * Magstadt * October 8 * part-time Senior Digital ASIC Design Engineer Synthesis role involves creating next-gen semiconductor testing ICs. Responsibilities include RTL coding, constraint generation, synthesis, and analyzing timing/power for complex mixed-signal ASICs. report probem [### Senior ASIC post-silicon validation engineer (m/f/d)](/clickout/83adfae5374ecf23?ql=q&sig=3f50044fa1fd575393a7ff0c8d1b785535338c0a&e=DfDog4NaePnRRlqEphXI6Dcsqydh6CjXPP7Yz7G1Aa5d7JHeE97ghEFVuZkjArSxJn24VgzBdxeUDDxB9Yb0ak-f_HCyhRHbTUnMAzXIRWtUvZ9ofxlMHKPuuI8mIsDSJGaK271Z4SyMNZvDhvMqF-QbQ-gnmNzeHoQwmsRg4U7tpIukFwj0NW6rq_6sxLb2N_JhkaqZH7h3GUsmkuSs29xS2EHZblzHTnJJHAM07CMvTus9GHN-TirAlUQNng6afiKOO-IiJFhv6XcJnifFENMzTvDSUM1WD4Ub0GJZlslRoTXshxO55EHFLw16OnlJJGdzlatE8_BdEtVe5pVFRZ9_esM0g8oEXNz5rhE-w3xG1kXT9lJdDcbcutF_jUVYmKRSUsE8ImrqYtK7qSXCFMpzWRfVkRDyNV6wg9XX7vi74icPWfzJx6K3-UKp3HAIlGkCMAR2iD_zTDvR4e4LpoutwkxNvca0KR3cn5sBD2pADGPY5T8yt_QQQzuqQNkvxCrNcBFmEOhds6sabS0aEiOEK3LddKFFeYOE4cqErpBKgn_T8vS9bZHWSM5UKyWbQMcHl88wZUGCJj62rOGtxxhD7QFn6kYlYwL59j5sm0pS_NdWjTsaP-ZpSx1EMQ0HtQs02bLCHI69jHC9P2-mKbHQYGeELFE6GvQegZSVo334PvtRRop5F1yN8iCigwEKGzLlRmDphzj6CjmwqSvv46UcKj19a8E_w6JHrefH0SvqnkwCy_8r_m7lCsZBFtE0sKR3gS05EMZk60N0XMBgb-d2bh_xan5j91-qqvvu1fBKr__mEzU4x85ACv9cZiz4uXj7mfvTo04wWU64NKI0sJa5ammVd8b35p9-IhH315Xv_vrDXGsMFQC8X_zgUJTzkUKAJrzhnHzBEk-VUkYdq3wqQiU6-pNwqHVBjcqdFj2bJsxvMVt5AOWdr5UqYTOy5xOgnWvjjKiNB6jPRUrpI-VRK89QM3sYYOJx1BzL0SrMKzzyrLTIPPZOXXcK86K0mfqHfnryjJf_LaNmDXQaAKTeM00YWI6CTW3TLtHePpmyJWY93jTN1HK1s0GWpTQxxCEzssvi4UXT3Vle6OmMTl6A4AhBQedN25t2fGTMkfcUEKb2e5T2str36g0AHeErzDKIH2e4jXuLzZqL4LR_-zQulzbQAMvrl2guR2X0SG0hZBF9cWoW9Ea1SBp_AUr2yvcSLpfFU-P_njRVVh-7QZf1Lp2FA1lfqQ6oSLYUOteCaYxLiLNlWJFu5mp2i_SqUE39xKslmbZXW6YdAyXpM9a11u4_W86uHXE1l4xX2ejDwDnr-pNTBrAbbXqYlyAjcGyjKKytkhpcUlK2N-j6u7xz9BEM04cb75Mptbxy34gNaPdWk2nki7H2YdPNLcM5aMVhIqbBTJDBmoX0qkvZW83xjARyccGzEnhf9G63Q1X4sJzdtM44aZmWvrwXhHPLicpija-agQ&prev=RQCB9E4C1BBCD8A7&p=4&pg=182) * Advantest Europe GmbH * Holzgerlingen * October 8 Senior ASIC Post-Silicon Validation Engineer develops and aligns test plans for ASICs across analog, RF, power, and high-speed digital. Requires BS in Electrical Engineering/Physics/CS with 5+ years of semiconductor test experience. report probem [### Senior Digital ASIC Design Engineer Synthesis (m/f/d)](/clickout/36fb260569409809?ql=q&sig=17de7f53d6fa0def7931b00bc52046a34b412cc9&e=mBRZ5ycAF8iZBOyt0kID2j_UQE0J8PyZNvqqP74qlCprTDTcpftcPrUdey8N6WobF34g194J8PoLTV6Q6jZuR-R7rrOlmB-lM4YxxJuvIOQLOXFmnExj3-i_6RttiBtWmzcIr-jlU9i8uIEDbQc0p5sd2dI5zI0__A2ifgDKx3CcySUqFDs8z-JfDc2BfqZJLe5fRuDLctReKSPLtxHsFubaUJbi7PqpcSqq0J45nrYXD1bTxAokieMm6j3DfTyq_KGRa0MILRFpXBSTc8teNL7jvYZ9iSuNV16L1kUVIUWlhOMRSZDDbln_B_2nbF64e4y2X0k9_46-8FPI40GgJmHMpW4nkjSqxB4MRVZNQF2xEmwQ9_notyb8D7TYMP0qfDlNCM4t_l4EW8eYxnDi6i7DH1aWeiTkSCN5BfyfuenfGpBwFKsuNu6ArSTROVklJ44E_vMfhA9_2QzhbI1JVPQ6hH4MpmJ7_BbJaSj_4C78xaidXGt9fqst-C7SCpgZiPGL6H_ECYFRUQy6KqdYihfcA2AAJCBKrydYTBbljuMPZbOW7A0WpWxq2WIdELWNdJyX6utS5y_Siclt8Efry0tUk9xZ0G-oDkVaUjyMG8JmcUGzDYpoiVZGPxuC-p3OusKZ1fKeCq82yXp_3wfUAgnbg9i5QPCEflFx0aoYCBcENRkCpzKPMAgInazlGUElK3pu3oXSeEbZMvOCLq-xg89CWkI4aNRA_58iIxpSSG5uwCX6vqRvOJSmKOzLCznLXjs-H8D1a6fqeoRz5AU12bkOsxEOqhKDlBu7sXACyFfzd5cIPN9rSsH6ycvhVAYMjyHVVQhYyR_7q4hAL705ckShHDY8ICAFc6lpvrwPdoW_603vmZG3kftKSWVyU8wBoaD1MB3RmozKSU-2MVhk5qX2cUUWU5BHyDhCWQ4pVjGiHpdWq2-lQT_DWa83VcNg9G6KodvHNgKa6GJsdg6EtUmpFFLphM_PLKQIZvGCi7n_ZQRm4pc8gbOtqfsknaPFEsiozXklYtlj02_z0RbJm26LquMYvgxyg8IdfwHEWAiwz5KaSz46ql1vmlaLQ_Xzx95SVAp4nZAu-MEmAoWDRLGazaVbCgnMI8P6wIla4gzky-RJ_A4fRgDIg_alVR3YdnZC9-z12AP4YmkVNrynabImFZBJBvz0moq3mRQ394jN7CWhn9y85S2Iv2GdLhETCG2p-Hg6EnpvFblgH4XbE9j6w5Z1X2k9v7fDm0HUgUda3JXHj55TNfoBn00q6eS0eZS66hRQpaQMIrM6DhT7eG4tLVWvT28NI8_E6-qVPKRdk4KQTRV45URTIwQKTNuYtdg_YGvHXUTAJkxmlqtaO5seIdkbLwkqrwzzfNyo8ReD7Y-zxFp5QZpbKYSmWRJtNJKN8_ivE3ifOECqx2cjMJjs5vMQ_KMHHDHdNSXsGQq2LnQHS2KIIa4AMSCCTGCkiCMNUUGMvlU&prev=RQCB9E4C1BBCD8A7&p=5&pg=182) * Advantest Europe GmbH * Holzgerlingen * October 8 * part-time Senior Digital ASIC Design Engineer Synthesis role involves creating next-gen semiconductor testing ICs. Responsibilities include RTL coding, constraint generation, synthesis, and analyzing timing/power for complex mixed-signal ASICs. report probem [### Digital ASIC Design Engineer (m/f/d)](/clickout/3490a40d1eb0d175?ql=q&sig=1752d142531808cd49505a722d5e52d1a21bdeed&e=tvh3Y401i4OZkxOAKv5Ov0Kigj0UmbDJ4N3R7-OX_JkSBUM0wi4lMu0OVbuEFVOUR5vVhN0tZmK95UtW8ZkuuguQxuxmmIvyEYM7mQFpN9wA3QqeNyV7-f9zugQPWGc2zYapV9iSdG7t1jSksvTZ_Kj7lQL6JILJiMC3LwrderUKrLYBkFDJFU3dp9Opf4nPe49QZtOoszH8Ou9p6JxcABV19x_3mZRy7AQOU_qG9yEO9vOhpuxKOTsb5zDZnppZCWsJULVkb1Mw2xYilG9t80Yk_85POE_KrQxmUCrdmcRi40wbH9EeXyWDjyfirho-LUVVPDEQBma7uOE3XEUCbCzshuK3ygfGYRzyA3Ytq0uL0jLN24z2Psuq8kl09n2rRiBk1VbQGusfaAxutWZo5XGBPwzoEFaLeJibFErHU37DacOP46ckz01LBobKNDTTofw0FPVHPbXLjBhJavQie7uHdLlHXDMyUlc2mnNDfQrPwMwmP1j2qng7t1e4MFlgFkWUjnyNy0P55IEObpqyBatA4lL3_5iFzjqz3lVn0SXv0js5ZOp-RGqnF_AzHyc_h0VspDWaCzcXHTlvEPSrEfmkUa-rvK6CpUd888NxoTvgeCNxt8c3wZI7LygPCM-R5g6huif1yUbrktQKXwhbua5GlFneFK9dVSh5HyMxIFsmQq6gCByqu4qXVObGqIPsBL7YCrC9Jkmbh23gY2UND_JUKG8CoDfaRylKFhhOri2MdMayTYYuE0dkLAbsRbcyomAUSzap65wK_FonU1p6c7ePUUHHsQJiyTU3x_w_tpJboyXbamcnvLoVHrfbk4yGFQNWaqH89ccY1_hH_jS1NXBVROpAw1WkKdI1QJiB4NLNsDghnTH2heAEx7XBx36SOZ5ByIrubkJgye-AjARIqlbODU94zrHat9bnbDnlI2OpY1X99TUe4AEbzfd8buWpWtGtEy6Y9HQ39gN4vLdwusfPCiQujCDvFzmBaGmW13ZBqRSP9Lhk8uUiCBkp2x6DIrNskkIurWW1iCktd1PbU8gySmQe0eVzjqy-Xk8f9agS8WyjbigH4NRkoSwug_4gqAydNij4Fq2Hax0TZOgFDq4GeRlB8SPjlp1_7SxJt08dg-6ePCPxxGKq0jNvK3kd2CXyNolYPdk5jlPfQCqXsN2VR4qu0ryinEWGYQGBZiIPSUp_RqoZhSdgbnWQaOYZP8hndEnqAy1pFB1VBj28kszzFegj16H25xG_pmAa1aIy6djZ-kgG7bjC3JNJdtt02LZ2Z5v7s1HT77ZriQUdUf5v-6lNe0tJ_1kvl423Lu2xPISdtDLXAe6cgjeTUtMRYfYtQiOLbDumMWAHrpaGpeotTB8b19LbuIY_84b6xTpEgpiNz1PPJjwxcVM7jKTprSowoJ73U4i_kttwvzKB8YOWBPhp1WApnRtjtxHbxJRx4m7k8droSw&prev=RQCB9E4C1BBCD8A7&p=6&pg=182) * Advantest Europe GmbH * Schönaich * October 8 Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include RTL coding (Verilog), verification, and end-to-end ownership of digital modules. Requires EE background and digital design experience. report probem [### Digital ASIC Design Engineer (m/f/d)](/clickout/188d6fa1320f78d0?ql=q&sig=4597684d46adfd9d609c6e1a5dcb9b021c1f0af7&e=CSaW9GkGCfYvF6TH7g0q_hEZls4UOcJIq__H4RxX7TH150HptPNmGMPQx_jCqvTTJ_24xx5VV_1ihIfttsFZUwFSY_UzqUpyeDzI-SKKGZd1spZkYgOqPZaJ2BmM5toH5TrQZOWcjpRsPXkxRGos4Ga1T0pC5tiKjanq90lKDCw7CYtT-PWsfiVmE5G7gg9_YdQgvnBYOHLjqkaZsLChvFaOL2EWmtEHmS5KhW49plWy1xyHxl_SnJuunEaSAl8bas0ZJlwfbDtK6-anTvvV5XnZS5rrosVd3xYm-eJC92F_z_8IulyZhYCDrma5q-4T_3qpKkev_pEKwQfrL0M1f3r_ONX1XnsmZ_FmZO_IKNXFhTJHyVUUazJYpVF_OqsaeyqZ8M8uYfqWY8gVcw5DE7tnoXiPUd1Lniluu21YRFampRF_2PP33HoqGihybG3H7-L-dJSW6qPL1aCBbEx7XniIv2sOBiyGjg82gY8CtY7HNuyvCN2FSYynFgwj8sG2huxlpXQtCuAhq44xZYd9aouPICVxLNwoS41UTwBPnkphgby_KsALScC9qxtedjozCwG9kofvHDl62Klo4iIJUJOmalEL8cKUJCvSPDk0pfeV8t5FtZmhW1o2QQvemdyZit4mA08pr9v53QSMCvkkj0KcrzO56Nj0rxdl5AidmAyqXIG5omzQsQFdo85jnpkkVZ-QJyuQryZFo2B6mlY7LDqE5-dpMRYksnztWkQbjZPle5-l_ea0IpzGjbAq-xRWvsJXaJ5CzsNEdD6_J9SoxBlCGUzCHX_sNu5CAPbdoESWe1GVBKyzHPwdTWp7JhIFtRteIs0ASs1TAXTSY4WmaWYeGt7elPV1yiiJjWPzuRQynhM4ToqZ7BuI2hA3F3fEKB7YxxNnsIyvW8YcLWJuaD6bUaCBrXy2zNPX4mPGiOxHYTGaIdblNvDxF9YdTQZXDHI5vOAymAnGz4tAckNVcNqUn_kWMxr-wGs83aHKQp7cSywbbawRyv-pYGGbrZ1q7YY4M46S_mvDF7lrg3Iiun2lhvFjRCxW5eyWG9sw4Z8Cl54ty6tsGbf2dynm-aJS2nUYk6DVUiWwd5uQyJroEwgnUCYq43-qctMjeP0y_aEZ8rUECmUCYghdf0ryrSAqNsWNHI1XTZ4gzp88qN9k7yhNdy9VMjzqf2FeEjDaP7LBh_UoUn4dMA-AnNaotDsbTD92Tanoa4E8qVv6dqsfaCCk3vjW7JQTibAz7ZcgEb7hzjgbFwJdzfNpri9bFrBd18xqfUNILvD7Cqyu-LrpSXNJdPX8ZAimgCu3IwRLAp1iq5FuqfJ-iqq7Jda_wC099finQn-2WMeMQd_JBcIuuoOHx6lDokAm2hSRUFhgoryC3rIxRRNUPdNt_6pOUiyzd3AXFr3COfKwitMHr1NtAkGZIwOZtoWACble5mvlIUK_tWo2wTxw&prev=RQCB9E4C1BBCD8A7&p=7&pg=182) * Advantest Europe GmbH * Holzgerlingen * October 8 Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include RTL coding (Verilog), verification, and end-to-end ownership of digital modules. Requires EE background and digital design experience. report probem [### Senior ASIC post-silicon validation engineer (m/f/d)](/clickout/53ffc72d6038fca0?ql=q&sig=98cfde273b1e7b0c79fdb8c1bf2845a2aea32f83&e=-ERM7XCvBARkJBoAyCn1Amd2AKjtdlbB0-JcF0DZQvSFoqH7qUInNnb6yABepGXjZ_0lOKTVv0KtFa5sGXrzZJjiIT7dd_xXHh53xwu-9WQ_QE0e1Qogd2JkkEB82LmlXOu5TRSlg9IF5npOeGt8Djp7wB5u7rtAi58ccroknV0xLC-qcLCoooT4IgFP2KHj8AWqKoc6bjYCgzTJKQseLPCs25w8KuBDP6iBbPyQciRa0HRrkqv0DF57zYzq7H1d1or6HIWrDhWI-RTiXp-nYfjMdAqJUQhZKYm5r4sBYWO6qdstUiza01M42N5ICSRoaqYL7BaoQmNMjE9PIW6LfYlGfvXSbFv_gKrvfdplCaeqyV0VZgT0CGJYQquGSJjkwf27dLoTAmbmPztO29SxGuZJ_g4sj-_65eWB1odYKsYVpK40sWlz3IxRd0_gM5PiORMyQAt5sPM5QkK7ApsRoVVp49Q-0Otopxf8rFuyG1T4mcDcguXFNh0fou1r90KkFxWK-YlBpp7kcHzqzc_1vDjWl_SQwcjXTDhlkYE8iPCQ-a9cNdqEefoDh0NvqaQcD18GPEReZgT-rD7emdHfH3ilDAenqJhgZoQtRMCbORNJdUqtwHSEdJedjxtI9GS8xe6bbmsLu5KK4LLfMlDc_LX0L6aMlhZmRIeLNCGghv7Uq0aeg10V8qdojTXx9Wi1OQpHhbP0hjZGdIExzTAhbaTq-Hw7sz-ek9hjYkwnw8QZWhwmp9TjgC0b3VZkQclBVPWFTih9pHu1m83lql442lhs3scUfX4X_xfjas5mjT6Unpsa3Ua9Sbc6mDzPVY6nhHhG5kMQeZSLctQs4muMfKjrl0lcVI_3-SXOh73LAAng53TTy24aqmpHW36cYCZY2dopwMIypSBt8Ee0JtPrKZT7WZEpGX_8c47wCjYbdCLVGvrzcnOT-bY3-F5RxEoa8vtGaBzUSkJcCRgWlSAiCD770wiNm2O1kY6dBBIEOiBOxKiKiFIIf5WHfXhVxAJmNMUzILSz4pYX06ud_jqsuauLH630Mhx3KEohHx6kIk-Ei33FSNnYc58V5KRyS7ZKps7-vFC5MkYW7LirhFW8NWI6X-xkwfJkp8MnMWHTCywNX5OvAU1z5bzPmuq03dD9Jz0Cu5V2fzYQRPyYod3GtrJ2pkyPBjhnlgJXbao55_2iNxVzA9E7O7x8G6zV2tYfStWutlxsJp1iLbalbYjD3HpAmv0avP_pdZQbeOcMYJQJhoKqNZ7u6ursqRmwCukiiZLMOyDCehZoDh7A1XoQwhj3-Mn4viPpbMGlAKjeOswH670vgQ2iw7vzmr4mWQvRDxy1I5Gpuoqe49XfqiNNmXw4MxKTHflhk_OYxNBZTlUhW-glcSf-g8J5s0OqFMAtb_9HYQ4nxgsBVOK1Rq8biufoZQzjZpJI_hCnGYScog4IUoyNJjuS9qgC4LbAErAsmYY&prev=RQCB9E4C1BBCD8A7&p=8&pg=182) * Advantest Europe GmbH * Magstadt * October 8 Senior ASIC Post-Silicon Validation Engineer develops and aligns test plans for ASICs across analog, RF, power, and high-speed digital. Requires BS in Electrical Engineering/Physics/CS with 5+ years of semiconductor test experience. report probem [### Expert Digital ASIC Design Engineer (m/f/d)](/clickout/3133141fa13d2fe6?ql=q&sig=2a98f9eb86cebe0b4475ca22fc09992848c013dc&e=bjolIqJrpDs1Y4w0gvVVYz5aR7VhDs4A-FudUKcc8cwBgy6UJIvz3hQQgc2M18uYPDd6VMEev0XZLBytqt9koimGPwhUulWqPcN_pvr9AaOTZH7P9Gmp2eq3dqkw4cGJ3zr9_7jMGsZb9_JhY4QbIWYsCFaU0-Gv8i1lkd4193PLlj9PvFC0zzsIjvYhqWtYq2JxJGTt5Rvnlp-uDOuBJk9yw89whhvPJtMM3lcrl8te6MLHd8U3TWbl9BgtW-hVUziW9FYcH_-sk0oE6dvUpVYFHnsIoep_D8wmJcplhZTkUNCPvW08tzIZsTdgk60GzBcGOh26ZqiwfVbDONIEzD1ZLVspX3UwAPxz3bBIAaVTq3iUUh0191-shAYd9_7WQ_Hbpa-hEZDXotd1BB8slKGp7JM1oITtKBFO-d4_ts-gLjms7gjnMaEFXaqj27l-mUCoM4xFzUpo5vh3xFVpNNIykbPVABRlyYyg27mf1rOfhJgT7M96nErdv_UFe3ZR01xrECgqD-k4hHoSZ_aTIvqwc5aj2y9tfyBObfEkwgLlsxC16QuIaZ2fjkvT1fiRb2E3oggC0ylRK3SCjw8x6HV0phO7knkzrB6I_4hQq9bQ7bsFKn8EeXRDCmkIWm7N7S10m2nX4nqJS2gnsMQcHHJdoBByQF-wEoAeA3hKvzzDVDyPgc-M4KoijqXUjwV6sNvQrSf7XunRpNzZRmW72XFdDeSTAWdUPpTvbGR6d5c8mmfzz6HwtpZzuKhHUup4t4I_ptBg4yuuwYe_rMWtAJcmk50hL0OV9g2GvTPjAw3JvpPlFHch12MFxV0DnpPx19Dv_Lj-mWEKNiO3G3f20wHd18ajmjs0RKj4JKiZ46cd_1BmYLt5gwSh9VWAkCVsUrR1H5bqKnIdIn2YmGTxmOP2MRe4pYHoLTqKliOqftbdAnBdDFXeXMSRXDhuFLxkxdmdqGsHviKaUbmqlT00sq0oeDnk9VgsAjB_HavKdlSHO-xUnG6bO0DGREfkKUa84wfVHg2upburMtcjJzqVQbt9Qm-kOMjpgKs1wwS4mbKKOsrhCohJ4f73ArT2WDM_6VwIW6VwETJRrTJjJQKyQ6hjXSZjuBxSgTpC61TGit6YVar_fVb77nyprf4q20nyP1wa2_m8tYBk997EY___TtYoNe2l-n_mK4TNJ3bd2m-pWOO9gSrSLIhAdijmLlSwABvYHz55rBgrOzolaeTx6b9cGvqQ06Nv6d_YP33jagqWQYLzG1IEi1FKbEp4RQAvk32RWnWHN0Whz90BsNfg7_qjUrIbhO-EuDDQNG53rHO5mTzmYXPZIqVdublvUlgxixs6Gw7B9hK5NtC7byhKLr8iZDqZgGv1CBN7PoozWdiHQe5oJUr1hchT2wK8ftaHqRnLWHs-j1wCGe9cZkXo2dqw8Y9a-AA8w1r-9u1dHP6yL3TRy2gOfMLQnUdL&prev=RQCB9E4C1BBCD8A7&p=9&pg=182) * Advantest Europe GmbH * Sindelfingen * October 8 Expert Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include architecture development, RTL coding in Verilog, verification, and mentoring junior engineers. report probem [### Expert Digital ASIC Design Engineer (m/f/d)](/clickout/112dc7a5c9055ea0?ql=q&sig=8332a7bde9dbf8e819a3f683d1e757edd99438ed&e=GO62GsQJmGLZ-_p2bD-JMshfGaWkND-YH-2TquZ50J4bcuU1DmJN_UCDeUFE0wDDvC9638JSEDuV3w2ORrcC6LDcxtZ8c0tQpCGVDnZQNtDmt6ic8RiUQgQg4Qkt1RSwuOE_YPuBOB_VL2cxMTDfOwwaUcAd_knmmsFQm4bWuZ0DIlSivGp90n3DrpzzvuZ5VtWHqxgFTE69JcKsJRw-1ChOjqyUKmf9S355NgYxenanTweDc5SEjdfVZxXxFGQLby4ZHN8pTO8NDLkPz-cl3Pk4LjfzQKYZ5FoaVG9sZGF_oStqvvn25BnDSLiaoRHnH0wMdrKPJCvchkJNY3sXSM6EUkPz4-L4dTXKgSQQZkI9o2BknGj2HNvKXMDLWI3i_oQa4IQrdZUxaKuMJQ4i3D413BJbAFcbW23mp7jLGcgWKux7d5PMfNHSEGpYoakQIjQy6t9IhTKrF8JA7AMXpJkGKfgsxW-Vk7eAKkPHKsS4fRqed9WF78bA-8Wr2sg6aakhestdviqMg_4J1cNo-P0ObgHTHjUcyr1WU5eI4rb3O4Q-Ks2u9hsdAbZBePXzZ3l9gG5BNvvVGIjExed56pbyjnJt4O6rCuQDjDWVTYkcoWRC3uxPnEeaaUF-UkEYgSw1y0VlArXwT42vhrR-lhgRxpkyIsGkrAGg6xH14lWiZICcKE3j71jHculNB3kUbifT_5rE16uqi-71hTJIxN3p99bNYPm2daBPDy3dfT_FKivYJLa1CIc53U5YnxZZPpfD8BhL_qD7Z4L23bqEznTzlGhMo9QtrK3vEC2C3f7ZqIcxQulxZd0M1ngpqU9lkx24m41Q7nx42A0tP00VGJtifPc7YG6FEvW0PRCnkiZb5oK5x57TeYaeg2Ec40ykeG3WO7sjAk1YhZIjw2Vlilb2zXmvkEGwDlU3U8d-GO-N7b2eC_brej-FUulJB4NtqWJAYwe3nt0lin2z9V0OPTU0Aakqs8ZMt1LaT9Fcf-NGyVRt43wqKJFmJYdZOWRJBSUKTWT6WNxOD9K7c2pUHy-EKthwL8iFEig0VWNToEfK-Yp648Dlr8xN_fKDkx7M80jTOEikyEnRk191fP9TU-o6Yqy2YmFj0OwJ5VBoKuFkd-EM_2sZzZTJqx34-5CA7aoo5jv9Wl8K2oe2ttB3A2XtOXvM7aJqtoSF6h1oZwV8d-aadRr7hfSuLTeuS78VX2MuZfCn05M8zFjnE-chCRUOjhWPJ74pJLiLv4popWVvUVCFb8ByApU4oNcaSydnYR3q4LODrE2-Djuu3cE-V6Gr59xPL-ctuORT-PAE9do9TiYpltfeAbzcsij5c6EEExyp4BFXx90pp9vSaPv0-T21cIswYNzPy5kQQHaONJ4ANOBXelmi1Q-nmTej6dA7D9t5t4JuqIC4Hh0uRHjiiCOw-4s1FjAmlupvu9M54zu6do8CxlbNDJE&prev=RQCB9E4C1BBCD8A7&p=10&pg=182) * Advantest Europe GmbH * Ehningen * October 8 Expert Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include architecture development, RTL coding in Verilog, verification, and mentoring junior engineers. report probem [### Senior Digital ASIC Design Engineer Synthesis (m/f/d)](/clickout/ccde26239327d972?ql=q&sig=4d2a54ebc02b1d1e9aeb5f50ed75500650d2c5b8&e=3pZifqG6O47hPNCvz3EDLMSCmVcSg7uJKujdN_MYlRxK9p-R7mAB3X0hpg4hg3_aZtOZQICtbKu06jy3Z8XiI_ukbRS3d7tMn1t76zfdAmPa9xDTzfuOH5I5HMiSrn_g0-B3nk7I68UhmgzfeutWb3kL8dn5N_Sx8zcIFqhxGWAVHf_oZ0AertGjs39bNsBdkhoj5ZU-aiKDGdw1Wd99_FvoIrFROYSRyqN5gBp4wUsBr1ykqH30dKFKtczpchiPawg240ZwyIAgVKLVNoxYRHwqCW5imiwR2qTXcvckzo2_SMZ7Nx_DvCWncKrY4FRNOqG3S5QWf-YoFIJHnt5P-6zgGGRJ-AtMvIvKFYDZstDdKum9dPHjyqFeYjqJC4Yc4_hoUuCmJG7DyBc7KJpIv-jlOdb--oq9vAss__0ZER5qjMR2YUJg6K6WuPG4Mj-2JZTcIMb4Dh-aVRoqZWPEyKaHtZgw99kLyZL3RrhSBB0IqKpKSjcAwWOMV-n3pSBF1pOH2Bpi52Qncuma8hW_ch8H0jeVeEuMx1gIxKMbTWXjDkmjETrXPIYAF-zWClVDohd1hehEv67wliN-z0yY571ELrLrfUIxkFP0xhshrPyB8mcj9QxRFNxXAxLBykk4f_K_VjodGTg1kDDI0NuzugjbzEtytbXKtrUwRnTBEUTo9tKUp38c8TCR0WHyqEmH9fJ5E6rmRsHEEheh49vsDb87fJo4vK5x1VdCwhgtWWNMu0p85VlDlWl4JST-cykJyb3zPEihcf__xqKHpQEuIMQwNZtKyKRTgk9_TLR0oQloXrqp6g1tVIS6yMisKTL6phHGeLr_Eeb674A4E8hwfX-DbJgh1GLFD_W5_Cqb57p2kxlz9jgI0I1t4pPNztlOi08VWRlJxRXZJzvsPN6WiwUI0Fer9KHpFJoojcVtUuTNUEcgZGgGwzpFUt2FI7rWf0UX7-2ycXphvyJXeYBB4hx1wBIv_eD4vghJu2Hnm8IMHH5rWGtclTRo_1qSFsYUT3CmR1rMyLsrrsh0NhSn0cZpI-heZ4REA3z5zENAz1bKe84teXKdGnEozicK0Y5gwZmf4L7BdVSFgDtBxjJ190AgdFIBuX3ETx_DSV5-T3bzsf53m7rZK1A23vzUBmlSVg1IMmL3gpIZujeVINYThwes1yvcZuwuBGwZrIOjQGh3AAn0yQoaGtt0ttHEm8xRtSd-zLMNvDWBWP5Hfl-R5mutCiPR_LRFhieV8kWGiGMRh7FRjcWD64WAVQJht9Z7EQ1m3KzzK5jVPnGXm63FMQjueIVbgxd8cjFffwVnw_gf8H5DRPuctpN6qzujDNMYaYnZ_WKSIcMRqFQdFw7cK0RFeq6BbdglHtNU7aJOktZ-YdutyzrrutowtjNvQDYdCMnVCHhTRUh-B5PJCRCJi1jwSac6rIiumvGjc20tgQZqSaBsvuUS1j1pPHuqzEInCFNw&prev=RQCB9E4C1BBCD8A7&p=11&pg=182) * Advantest Europe GmbH * Ehningen * October 8 * part-time Senior Digital ASIC Design Engineer Synthesis role involves creating next-gen semiconductor testing ICs. Responsibilities include RTL coding, constraint generation, synthesis, and analyzing timing/power for complex mixed-signal ASICs. report probem [### Digital ASIC Design Engineer (m/f/d)](/clickout/a37a38f172a46a21?ql=q&sig=2fb3c537bd178f63ae9c25d842b369c384841df2&e=37NyPQoa_GrJ6D69Kegd4jd_gQ_78fjCoB8hM8uIIQ2GOMHBX9QDJixVsfFtLhEOemkeIYaH5S00McI0fD3YAoRa-ETqAp7tLJxibCpV47dmhMIhf9Zf1BTyeMeKbHYiSsONhzftW4o3jzuBv7JLSWccmw1o1N9EffAERDeHJNdPO-IWtj_cA0CYRQBcxyDT_JkxWfHqYaaexb78DtOe_dHIma3KP1__lIYK5Zgzy1FZ4s-q2qAg50GU7uYf6jhRcYPrvsGK7_3JEysxH8Kd7idIw0fvBLS2HrMY7m3f14dsc_hEngiep82_R4h1dnmsAlvKf722Cv_KMrbRe-uKdwI2otrfYQqENBBoLDesuAkb3gacG072l6qDtOvkB4Ze6Pe7LqOPq2a2JbDwiDs2fC4Jda_PE5nu5_9VqE0X2sIsV-oWeXkK7lF5nFQugO9JvXFs-a1PGQwDkgtOMZzg_935V5fOjeAEZ9b88cKsnMFpvUd2bgFLpKQ0xAuRRSAgmGnmUzHIHOBnAObne01TWta5ISwhdbI8F8PUc0BTXYPbr0cqZ-ti0iaGdhVq_htQfFDmEspaPbY2_ZrZIRjuLn6qjt7MuO3z8J90yezCR9m9nXB7y4g6CYvSK2s-TYgVvfDlsL0WSVhKxhOm0ZMDXT3ucR3N8MNOt-sgJQsTThQudMuAN4Fs1B59XAO4kJT6I-2Cz7aR4vzjPhe5ZPO9N6cFSwCC85AKitP9hvWPeNZtDeYCJt5oMvw1i1NpqfWI9wmoRLJImWa2PHw8nPewmwrrJl7TDXADkz3lymrEzEPPJMM_zBpCZMLH3VvSr1qLaXIz7mQDsnvNTPVnc8FND0xg2v_XPQ9H283ljf-MATJkud4l_ZvkkExs489h5tv0Bffwyx8yEHa0sSAcVuAvasKcEw0gcl3Ts__7EC6QaahY86h8NwnSxdSKFGYzkXm0gz8To_jFVMlc2Jy3S7xhcuEF3MK6ac0YPFGcakxKK_2TNFVx0O4pDyjb2VUdnKqvjnXAJsA7gALpk49aFatAMwTG3W-4Y9tsXQHNJDSsPzinjOwaUTe8_QFLfoB3ykoVj0e4dzS4YznC0xYeUEtNXHyrGRfFDDnTVyyxC88s_ONjDpm5DFnGoZJE7CU2BfJnQ-xGX9dHoYSB5zW16WSLh6RjKB2abH_QCfCE0xBoVDXWJ_faTZuRDMknfCaS3a_DJ-mZM-m6b5vTizvX4QZZDYzcn5ftYOVLurEb7kCt4zcfANN_ywFeMzr54jD77WuYvLwcA1ysTmS1oN6_AdTXugjitTvmkMoDUSL9UIH-OXHn92ivdHujZfp7dAozjOO6ROXQUbChqSCbNJ45Ri5Ai8DdwEHSA5QFWsKLNj7vpFW9kG7Svg2KZzf_UFFTBOeMMFgDkFUCiBASK2X_-Mka1eCt-gTNQ234AHOuhro8m0rLVg&prev=RQCB9E4C1BBCD8A7&p=12&pg=182) * Advantest Europe GmbH * Ehningen * October 8 Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include RTL coding (Verilog), verification, and end-to-end ownership of digital modules. Requires EE background and digital design experience. report probem [### Expert Digital ASIC Design Engineer (m/f/d)](/clickout/51049fdc7ccaf42a?ql=q&sig=6d1348a76c0a58551b8849fbf190d4cbf598a7a4&e=IQsYHOq9UlCw1WtnNpmfP40sruhNYss5Gf-dcIUKqEPQ-yvjp3GwyzoZhk4U0gx9jH8oq3Pp1GtgnU7mF9j_PmG1Ewyzy-E4cCaKlaMJPFDeXUHFoztIMNxntaxTzcmmVNgwDiri5DI-CaXKM8Vz2XHJWyOMjI52CD_BLTbwAbSYzlONn6eYu4roqKL8dFvQB9L1MOFx5yo5vJpcNmccqVDTZ8vZmk9jTXLFoASPbIag2WOhJoyx0fGRROKc-JosdY-CyCAiPFj64gDawKmCqLolFBWSpEauV2oe62LK4ErpBmKqsRfHPGr9d9VmWTZ0SQJLn8XFyqzHMM-F0iK7avTp12fKwFhlxPcCxTZoSRr8JrACIbrr9WOYZEO_uAIQs2KxurY6oeURwFjCryXWCixRtNq7-otEiP1JF7UOoImK-c834sMDvMFJcaGDDxl1eVi_hvdtCDyXepu5zML8iEwcif4OEOOYstFzr21qVr_JtSd4D1seEal9armZYWVc5H1F_X4H4X6yvONhR0gY35Q-3HBmgHmgDTOpAfa_ozALhv1-7KX6YCBG_GjfevEe4g9mVS3P47AbOpR3mMMYVbPXeWzTJB7V2dfxodZliYXu0fYgVAFVDWcAf3iMLbfjEQFsIb68Gop37dvtE9oiHXm3CfKEdK_srSe0oOMCwHUn8JXG_CkuSo1h2awZHtWuPiFJ7bjSSkuhxmJxWBleJJbl43wQqkA-1AYmiz3u2232JaLKQTt331Ck5zgloUXQz2YQZ3Mb-pVcEVSjv2TarUxAcg0yw9u_HPv6mWSm5nFr3FZNVivz6X_XtyihWL_UV8Eg9iPYmwPhV1XluPVice0geVH4_gdFZixvftOBmBPnqE_lIZ9mJubNrNLzza-jUeuzkzrRQcvqtt97Uy0daYjBxd1a21CS5ngg_M49f_IMejc8JH0v2yCYBuVZyxBjwKfvVCKZL4JlcPtQvjS9Tgxq8yh5UA_juo1CG8x9uxtb8bTEx_IDFzxIjO6xEyqXFVedBzs8RDYm2mG4lFmoPbs2MD2dKg5XFktjo-qWSac0saWkZUfaP70x8znh_gu4Lo8KpRclQd_oNS5Vrr3w3tqprWaoYz6RgcVnkc5xj1JRuSYlAYaHYvvoAhkbUpuEt_VUOlsRfiddZqJhQ8PHda4fd3ubO2COBMB-dPVFiCFXvvFIFI3mmBb1YNbYpGJhGSjcVCR96Zbxl1N2jo7nJ-fNsBx-_fHtHpMMGKXZdeHlcprH8uGsvkAXMhrO6CSk9NLpdO1dHjZCUNOsyttkYLFJo209hILvHTG_wRhrMnMqy-VXBAQS1-vfBBpXzm68-gt-yrS8ChrmYvgpq3R8ITH-0e1Oi4CcNDS72KPHQnvskACjxxfPTAFhBYM7n6t7TEeeMrLHuD71hhDO-G9VLuyqtkgnrcOHMc57-4yediC-kF0ZVWs2ZO4tjfrfDtU&prev=RQCB9E4C1BBCD8A7&p=13&pg=182) * Advantest Europe GmbH * Schönaich * October 8 Expert Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include architecture development, RTL coding in Verilog, verification, and mentoring junior engineers. report probem [### Senior ASIC post-silicon validation engineer (m/f/d)](/clickout/d14a79001b9a9917?ql=q&sig=041722714806259684161b56007d6149f177b4ef&e=3MbbgIRceXxbY2HdRLDaa8snEa1bsYvQrjtkmGlZRsHqhu5s_wxbJ2CE0w9gQGAVDBIQHiMTPMO3sjHHPvvRsyQG4geq5h-tSEskjNRTkDxHsZuFP3bfXMJAu07rDYkJ50K8FHW1HGQoBohnSbzfmGsWE-vXL2NG88DgGRHg6ke4KTGeoyedgq6FWqC1CbTnBDHPeNZo395pXQeQvhI0AWTILtbMXCN8XgHfn3XP4LDS7pHmR0b_gU9-kmBSOuAb3tGpvbjfZRCQyq2ibf79tL6HKP6G0FVsUMP4fo5itXbR3dOpDrYZNqH6p01GMkrLfWziRt9kFOXdvduAaB8fmUBb5eTrARYZLnAEFth4ALPPiv5QcNx-sOUPYOo5WadVD9TnQlxohoQGgn5frDF9QRM4Myp9c2aTyo5IT_XfYbrSyXusTLlOfHHp66NbAJVU5y4TUZjhSeyrmhNcU9PQYETduGjyDf-x-WZt0vSvf7FmneMHhR5h1vpXdgI0u5616q1ZggbkljWNC8aDhK3jq5SG0wMBjDvhRuZw1RIWpHj1zPQdhbu19OakD-R-iOiJeEmj9ckFpPUxHV4i2nsnd1dbiWW8ujSaYN8tum-cRHV1SQXXWCkdK-xi_C5EX2rT5t49lfNp4Rf0FtJ6TgSe4vQGXRmjshDPCAdUdi9g3IwyUS-9XVLuFZbJ7tZdBw_CC46on6a67MwolhHAIPYjrC3X2EuGFq0egzebcxeb4yKqbCX9h3G9m2Ztw-kFmPnMjQgq-2PvX6UCIWqE8bwnqgW0Yi95qphTsXUz5v5jHeiwCOzq5eqv-1AIfvoV1ZGgtZWUqWoWn114H2n-VOX1ktQQKzolEmjSt6oMkqyWWRdFbRrwl_1c02kJ79lWwhygsZod3rHqg-izFgA5A7rmEd8-XSriFK3NtLOY0LscMt3yX6TmKC1sl2tNlebg5spUQLaDIT5lB6K091DmJ4l2cMbZWlebOVid5MqUyd0AuNF5LCJfMp9D4J3Fzd2AS4yqw_WPcdqpFcwSu7OXpG7XEQ184SkAfyHVwTW0HNnlpYfqjx7IYH4jsS03hXoqqltvyLtt64lAqF7-kRp05Hrd5d-gNyKV5oIFL6wC71zFlEKx6nbebvQK4A7DybKRB8yV0HWIjWN9zUEbRi0qnMhl6Bywp_yOZ0dBZKzSpB3_DPnrgDmzDnpNU4g4zNQkNXdfWL7dEdhpWyFV9BUeZW1cyTLGGTmwCVT_GrI0-Onj3QhhHis6M0GP_5LFyDd81hur9_jD_YbZbsB-Nk0OTSDnsS9_8NpXTKSap78ekhHr_16PfP3k3VAKo8zvLoUsfjShksTqTZTw8mi3fEdhLL99Phvz18bQ8lc5UN3nakd_UvrguQdAPSXMTY1514nqGvte8kAdXqwuhvtoFOjpWqFIA00hTqrW5vi1T5Hw7Pgov7MXHzNgbhWdqRg2zv0Udm9e9dJ1A8A2m00&prev=RQCB9E4C1BBCD8A7&p=14&pg=182) * Advantest Europe GmbH * Schönaich * October 8 Senior ASIC Post-Silicon Validation Engineer develops and aligns test plans for ASICs across analog, RF, power, and high-speed digital. Requires BS in Electrical Engineering/Physics/CS with 5+ years of semiconductor test experience. report probem [### Expert Digital ASIC Design Engineer (m/f/d)](/clickout/9b51d2cd468e9b5f?ql=q&sig=5f7c018059190b9fd6eaba6b138ba372c96d945c&e=nGJUQT5T5n5BM1yA0yPS0Fd9m6eKFSBnzOKzsnEBf9YviF3ft1mkhDgaOm0ex99bdsxpn-d7NZvynxVB32sX1QQjidZQn7uVp5cJdrWOHcBI0R5QRwXGs1lX2iy7ogbhv0nXVCtBGSDJL1_X4H_Mq4V7O5rmfwQYPfp6RZiNnexlYh67QpHwGl1yYmKAWls9HR-0ek06DGL5oD_CPVRncVm0PyAbuSzO6HkSIe90l_bWLgJZDpnrffI9r3mSYmXjPuql_XF4tzvIwFeN1G7IUyu4svJBOwslxo1EQVrPoja9EPTAip72ikFJrYFZaCTBdPxQ1MOOrR7ZoKz545uY38O3kgZ7KQBqvabFiFAH_IADC_W0vinO2mVKhYDO2j-6sNAdEeudX8QsxHo9fWj-6kSP3gXb6bgXzCnjKELHvlcp__wQHNxNi1oCqIO9zFLAaPa0JeV5ba6lkJFRwgyjA5tI4gkocIGRysxrHXphozlB-NVtoVBb_ohXTtz8i8Ly2Is7HG1AtccOrnwquoMeaJlq3wp4TwjjIMNEDefS_w19cQr4jY49p0I6ex-SrtoZl3AAQI66tL3ZdBsY6WEFIpN7NOwLskFveJsLDeGJu4iyQiszWhkLd3uce6-xUo4uI4il-AcDFfImsbmJEKkgjuRcvo04rKjj8JDdhjE5Gj6xu55zsfFoo59TEe8yaqG4F7t71uC48cPnVM5eBa69TtySkfMovbotH-6iUhs7z1XwM3iSryDPQZBV2wD51J2NMBplYLyvlzuEC7ZywXMS3Ge3OFzaGIQGoZh2-j76FYhZN-bpoP2Bh9IJiMmArLlNE5DCDqr4ut0K2iBrdi4WXpwgpW_8lIoGaiY1Mza1JOAmqKbfc_aEm8lDWtOeZ3ty7qp8BMSjVkVpwbm76-1FQnqXGIgI137vG0wLO3n3CT_wVFmwqXEF3y076Nf0JcqbSeoDmbhK0Tp7JuWx8iRNkh8gi-Nm3d16jk5YUoc9d3nk7VnU6UN8UU5ZcZMMdlBYfGTyVO1PCC7cJT8A11LkR6cTdry6YR6SiaSGOpKfuuk8hIq8PhZkIEDrGLJLpYsmAx6jXpQdPT8IpSp_SE_DYYTcVK3JlSfwvB_Kx9rsxN93sax9_11t44geaIHfzpu2VS9cDTLz2dExAbOynmKsGZ9ao0LALbfRvSfHdUo1PSklo_3NZYkDHSRg5wIQKUshIkcOD-v_wkCLQ2XVHsKouY8vTjmX6W8dbg8wHkFcOxtg5sbvYbV7-mEPHOfqkB_U7is-lqXqaXU5qtDf_Wv4OIkFc35bGrP67zcYZaPQ0xeSQcnW5z2bKNtBYPGoNT3l7oImoWHYs9ZMuF95BQPzHZQ0zuwh-IDbgtnWX4ndki5EguOshk3Y73qQiUvcU8Gg9rMWBaeXsmhxSUGSjWNa9SLc1aiDC6pdmr1KrNlNK7pP_T6qLT7B-rZLg7z_sw&prev=RQCB9E4C1BBCD8A7&p=15&pg=182) * Advantest Europe GmbH * Holzgerlingen * October 8 Expert Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include architecture development, RTL coding in Verilog, verification, and mentoring junior engineers. report probem [### Digital ASIC Design Engineer (m/f/d)](/clickout/338eb15c1219a30b?ql=q&sig=5c8ae5b9b7a755d9f68282b2821d8ad5525cbb3b&e=JGbjdZ9kH88NRvEMaHCLERJYisH9Kt9k0Z_kVQOePCcJ9gpHRH99J6DUxNLWPi64UhQz0tDPLAGvpjbrGHNCFhkoGwCFsJEoQN6CJY6UrcuBAjT16IjI2GChWX4lJlTemQHobdOAImHEz_9TrSqxYYGTuVGJNflzCFFS7wZDB6NvRN8yG1J-GpfFr_AGKxBKuvChMK1p7kjepPpij-cTaPRMdcHtfQR43S0iD2iSieP7EX4R5NfVCuVE_W4OWhI1p3wOPva8x-Qdt7eNF63gD3wxw3wLaKEz2KtCr2BmjLS86CPdiBtroW3aTRlfq_9XhXMCHqtW_VixaWjcD6V864Oe4QmL9Kx3-rH5eCV7p4RROKvTJctzHWOq4Cdp1gUK7vn4AQQ4d3cIV1iD9UmOmRkRAZFzzzHT1e2QXZdR4CDcQq-XnLSfKDMwQSgCmFDSdI3e4CwkmGX1OAFLZzgfC-RrOGn9Pppsqor-oRlL3wOrtEBuBT2CNTtY5Rj9Ov58uu0d4e0lln5HNL4BdF7zx-kpgoekqwlUYbrvPsY2yfnD53572BkhfNTbsfvuidSS8B93yK4pBJFrFsZ4-o9BMwn0fV6tfH3drr9b5i-YyZOPDOl580WATXNS7Y3DiRQhB8fU2INK0xYg5oN7KWgBsU17S5YGQFMZCWbf43uxULg2wiaknYQKd76RympMti7QmZsTqSCm-ApYwhDcs392ijR75dBBU9wFsfJuGiuHz4ZQ-Q3pTk4xynISZUw87S4EjEqh8V1jqzL5XNbadJtSH5IhJvMXBuwoNKGUUF1S1FIxU2P6UEDv2FD5mbG7HeNshBOK6azaUXzidyaVEDdida8ELaJM7AcxF7N-x-MynLYSClDEAHUBUgs_o0nRzvm-f03Z5DOs_0BD2dn3h0pXKYpBXpB-FVws4X7ncKyPG5rJvZL-B5UbkL7tKsObbUgMJZrG45wJkLleAhdxUcVHYl4A7K0YbQNxbTTqYSRfTpf6lmUjPSas6W3UGr26FikbvI5vHOqvUXGTIsKpSsLDhHvr3LaMetT8BS5bqwgqQy_6lD7AfnyOryoTT7Or0DIMEs9uORt1-DPjqzlM2wXa77OgXLbRVL4ggrlXoo_AROhnOx-ay7Ah-0CTRTJ8Qi9WMkKPU4X5a2culEtXZ4RFc2Z0yps8KG5FdXretlIIyTGWwHZM4h-yhGeI5dyCTKwztkSwVuIHm7_rzV6aUONhbJcL9DCuZGkE0D3KajrEb691P2pJDyXbd4A4VlAd6mMMy1blLel54Fz9wIFn6ks_WahdaRvLnvKPdzqMAHuKjKkRhWUSHs1EEdpgiexxiyYV9623MgpZ_AJMvuOvbOvyZfRrE8l3azgRh6Is-uMRu4k57dTlYegbVIzYUH8VrvVdDpXy70sNH3kPV4sQ98T3M8nMM4g3ykXfOFixXW6fEPG1hw&prev=RQCB9E4C1BBCD8A7&p=16&pg=182) * Advantest Europe GmbH * Magstadt * October 8 Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include RTL coding (Verilog), verification, and end-to-end ownership of digital modules. Requires EE background and digital design experience. report probem [### Senior Digital ASIC Design Engineer Synthesis (m/f/d)](/clickout/a5dd1c7613bac93e?ql=q&sig=106d720720324fe0cc5b8312a04e56c7a49796d6&e=O2FZfF2ODRw6s9HHLttCaVQxl2gLnTn-B1iTeVUvxz404kQ5Nc4RXQeyBYvdAuk4lBVzLod9fudplvVg7r1rH7T2QMMydyV_WShkIof3VZRx9O9XGLIy2XAdFoZPWSyh4fVPWjWdyaaHxS5aIgeag6Sy7bpxK1cKHWEz89cJxRp2KafgGJEOeNpEdGNSdbZTxPc9FjkKIDEHNIzK-e7CmB9XdM-mZ62f2c1KKJk0M2BCGpEcdC4WpXDD9g18We__rl79hy1gk6R_-thoZMQvUFEOd7y-dGRdCqqi9lqDlMdwmuU-VTlRahRvJgqgZPQiJHA0sR__CoOyfHwwqek7GgmMsQorYTSAjJZr_I-JvGxwtWSAiMueXVlmVUdT4a4vFkhbBO775CQfcnz-TBwkyp9g_SjtTZpVdlvjjkOZboxxHV3hySxS-5yYm8j6KHd_AShxCJoXR7g490V6Rh-0rjcbYFjimSfkSUow6upIeEUOInsMttsTj-TVHym4pXpHQkOCDYfB_O5zhN-v_04XAkMqm38jFhahRqqNMVwQiIhnqQ1fcjqO6Kk9k5WIs4x0ieZMxtZlzi1IFPesUmlm3QFh9aad--yYGHr9KEq-rk4va8QPY0JFMR1E6oI5DtrXil0oTePiLTL7JYRERQPzdzXzPMeB4DUhdnchg27WCOWWwOgn43X2QH3AdtUIQfle-oWieW55qF-hwDYWw8M1oq4kRoAcBru-RfzowjwYkXujy7Igi2Wi3n4Dk-Wp6F-cbryQOy6BGQ1QaH6Q7G1uA3SePwPWSQ6UFcizjci6D0L3xV6Q1nmnGssFfwKvB8X3bpnYW5AcN2cZlsDLAKVkSMbNiQU5SJHGDRosktLCiC5sS7fRfNPnkGslTc1znjjgj0smZRnMg9pWejQZLcQVUbqwTmyu8Ia4D_n93trcTvMz7Azw6MDRlsLeQ7w0tF11oXzKYqL3xzq-h1H_iSYD7jEyRotIeAS4udeOhSi1Bf75JR-WyIP2lj0OlIi2xUxSCNXJVl9tqzf-hZOL01OtoEBMk6NQUu-pm2lkK8fCnhCJmutT4-xST5Wh4nwqnI9wkfcqFSDmMouI1TpgFBo0jmEwmcSWUrj6T2vK7OnFXuJ6w61H4OUObf9eqWGyQAVnX5t2KpU_hW4oTU7sdN5LBO2sO7JzWmgdYC_goinpsfV9P3UczlTzIQH58kh97lRUAN2P5uDgyXdt0mqzx_hr5QV9DqwxM1qkR0z6inZzgIzfuIPV4HT-Vzl-6HiTspf_cY9krGDghWwNbfT_wvOTg4hsd7LK3cpa7J1Mkm7GoHoRTl6puxLU43PA1NIlH1rIqWb_5uKjdwQfV7Kt-7P37D7H9ZwghLSh24xiaFkjCSxYGJ2QBJikpc0cIwDfQvEKKaDxBRp6HPCTjKG6oFjXDSR3Ixt0C0C2PGPFcbHgbwY2m4WLFJd53imSoV4f5uCz3_2mBoy4yhaJ&prev=RQCB9E4C1BBCD8A7&p=17&pg=182) * Advantest Europe GmbH * Schönaich * October 8 * part-time Senior Digital ASIC Design Engineer Synthesis role involves creating next-gen semiconductor testing ICs. Responsibilities include RTL coding, constraint generation, synthesis, and analyzing timing/power for complex mixed-signal ASICs. report probem [### Expert Digital ASIC Design Engineer (m/f/d)](/clickout/deaf474a6dd00250?ql=q&sig=3580d688cf38d936b692e1eb84796aabc581db93&e=hV90ocbEYD_D3HrilwAq0UcMkXtFQUCsddktEyol30-dPZJv7nxaCz70bcm-0PW1eKFvhHjsMxsZLuELIU1wQ2PVdhrpKAbrmdAaSaYp1CTJRRL9owBmSk0pqN7Q38L8kZC24TNLZVKaKAg4-uIM0sbuq_LdShEOHDy_hn307H8uh9pF8aQKeyffrx8nfvHviqCH_4vnh8B1XjK-cRv3V1coe4rhnjUV5n9_LjB-4lzVpQn3Tn13855Epy_iPbC2ol3ugvYjPfXQmSXMW00Ub0Swbaq8JU4H7v20985WtTKYwrQIE9TCLlIQUMxugyspz-Vqj8Tt_vz4B7mlvJqTmlq6-VDOKdCrUmUIrHXiEX4QZnB_5hZZCUcOTRWJWl81ZK6w_IBbeVT5nyN8vGrbWB_nO18PqpsWvsAH4hqE96422-Yi4vxk0izxPueJ83-B8n3TZmf6OUNVQvhAEj_Jf64-PpQBmRUn5OLCEqe5XHdKMOBdTpR85GuRp3LgPoh29X8zx3wHQzPQPSgubOSSV19ACembQnMC_mPtlHHFD0kwrFmGa602S9g_PkDztFBTnO-_Dkbj3u36RzLkBmeLZm-b0rrT6LWnsAYFV9AT4qxqy1rRlHJTKW0hzYTg_GPdWOpSpPZPajLFhXdBgw2QzqaEu3DX25xVf6u8jzpYshDZgVM68HZCr90vLiT1oUjUYJO74p6w5_pNDdgxyyfYrS6wx1LEUygUefCnhU2eHyp3uVUc_ZlOVSjPTgWGfj_1r6b0n9fvd6SNFItuX3eOpSBLRbzEv5qhrCrC4exEXT7tzLN7honGYGdrRRH1PgDabiZryRfLjLiI8Bcy3YJTTA92d9WGPphuoQZ5faw3NKgWpCceKU2Zcg0QW7j-W_LgLMfRfOQjV3bpVvZ7VAT4Ctl7Fiy_JJJr__Vbx8MDLsTJ3el0RuL2jb-MtPSsO-03HdXkDQhxh7AJ5cg2lCFXCl4dMYcYu_K4sXFiZwx_Wsxs2wX54BWskGz_BitBADDeoyIDs95tHsP72XmvlHn_twSbQnKgiZ97TeT3wwFQCS9Gb5Pw3rHItQzz-qTRJ4RirCaCi4DEwBUYliQ9jU6mPbfSSLSG64H6g4_ZXg6PZsu3v8lrhrRFQPfcXq5b_mDFypkbtXRTstsjXdEgAIerwFjvG4xGr8iufSRs30kPtiEYwZIX49c9nVi8dczhlW8YbY98_xqwQLAWazAZJoDa9c7qxuJAb1lQc5As8AiKjn9wUkBX6fiaYiK0FAmzhd739d_gxBIIKOVrSYA_wtzODMB9hegWkJM1IThA8vgfQnHgzeUk85oIj1JMunSKOazKpwoBpGTIXKgMGUkLdYil6tVMzVPSTU5RBTVtnq5cn1mM_KqBJnSY_wrqka7EnNrLyrXYF-Qg4qZ75OFy4SzfVlsKnhMfUjTmdi9AQEPvVvQGAmhudvpYNEg&prev=RQCB9E4C1BBCD8A7&p=18&pg=182) * Advantest Europe GmbH * Magstadt * October 8 Expert Digital ASIC Design Engineer to create next-gen semiconductor testing technologies. Responsibilities include architecture development, RTL coding in Verilog, verification, and mentoring junior engineers. report probem [### Senior ASIC post-silicon validation engineer (m/f/d)](/clickout/180c943b89797b83?ql=q&sig=262bc80b57d17121fdaf10ab5e82ab09ea239b21&e=SrTEQM6YMqSwnJ7pKlhsvy7XXWakenWi2aN1eTrEaCznMY6IME--hxWgyL6MGP-n_WiISixFfbiXuaMahJHlBvR8d2rxT0nnN-BSyqySyVtSH3PLgdauNOS9sxyfWR6hr9ZTzFUdBYRr0WfmomvDYtvxZePbt7YjYHU-KxO77It_Co084g2qM4nN5YAKl5r1oyEEUa3XtukY-Ma6OAKWl07QLQJKSA459cS45bUv0hMExCjIAjETyLthdGEaReeMWWALzLV5pxKnjxtZ4thLn_etPXVSSrJL8cs4xs2-nNIeFM1IUceqmtQuOLOhSllrrxHVSPf8ssgkZY8IUjvQ6jt5OIAuzm4rI2lmO9miZ2DzEp9yCum2JuElpAdEcH9tsIOU2LMdWXcLX55yYgHXp7ZwZJDA1YS_2o7hD4gX1-EmwVlWRd5YqD6nYLgEHERZGn08W3cUPGagafM5AxoI5eQWfUTRsP-VBs2AASlaaaEVmxN0Vd7T5Ph34pJcJvB_k11okQf85LHK1ZOR_lokOBwpv63cNNfk7GJyLDzb_tImp3Zwaqdo8L_xG4QqpXaUQEpD_3-kmaNVRPzf-uAbVXPwr46FGKWMiSR-IRTzrDDTDk1tA0RO1ZW4fTmeE6wp-JjbrxBuMzcYQo0U7z-d4msvXNogML4Mv8Xdep7HZ3O2EJaBYa7kQmbLCG3zlMs5OK4E-qwSg2XBq6ts_adclNsryQZm8g9rxVz-jPrl6es8OR370kZamNizDKR7q7jua4ytSc9xLJ6EvxvTIQwZ_f-Fn6PxqDzxc35UiWZ5Qb8mKwEgnjNn6LAywN8RdTbx8Wlfhpbko-0ZO8nv9PWBGhDL4NKG-Kam5MspijYEOrKPAOlwTdFTKhaHqL701AIUCn8llwrS_A1-dMT5VAyoNLjAjAAiD4I3D5UdsX_Rnk-p7qft_SN7i-h2DCbQDqQOFTqF3oSWuuUi_GTu_HnSoq4m7uk_t065j2P180f055D6qlWwYVQjkWqoIkhDcWB9CIxBFOGelCH7Dxk22lw93LKgKrUAS7Q_hTw9EXr5x_ZO6IxkTf0XgB2mMzRcbFU3-UfBLf-DYEfncMw9tXc-cBYw2tHkV0BhtHbk_WoJMoQivAVjKGspf7wcjlWcXqqco1K10SYTKvj2abdlpm_v3hQJCHtHzhZ8VFt1HDxvt-lqaRltxiBkayA-Y0u-RwZjdcPZLYY58PGLcwn1gNw4E4geUOc8Y_2V7VnOupHrmSL8A7eurZvYHOgukG0l9CmeNck3rtZBLsY1ZvnUNKZOhecsdCf55RvW5L78CfWTYS8EYmncIChUL2bVlo4Nz3VQrZN0QB2ePpKgi9JCw0WnPqODiC5nrXcnQ58ZSGuuO3kDXzc5ixqacjZpff0ZSt0ygcxR3oo-SPD_-Uu4yL-5yiuMq1tLLD0kpCl6z5P05FbtEY_MSEn2hBZFh6yOm95Sfe8&prev=RQCB9E4C1BBCD8A7&p=19&pg=182) * Advantest Europe GmbH * Ehningen * October 8 Senior ASIC Post-Silicon Validation Engineer develops and aligns test plans for ASICs across analog, RF, power, and high-speed digital. Requires BS in Electrical Engineering/Physics/CS with 5+ years of semiconductor test experience. report probem [### Senior ASIC post-silicon validation engineer (m/f/d)](/clickout/b442291eae2bf7a7?ql=q&sig=c8e12befdb1ac5e6a58cafcede331dc6c153316c&e=HZSi3Fhev8lKwr6t-mFD61MJdws3bro5gFA_eYrEh1kVG9g4LDVHpRUuFFHB1oacxCL_VsampQklQOS4wRBfhohYJad7RICPDnGbccfiz2pcjdKaG1uLMMILiRob_DwUQrTeQAQklxYAzFya2EpTVMHx_ui8d_DevyK8FPqaNPKvktUDvBKblxUW5vZpAdLIS8X0QuOrPnQWy8v6V7vcC9JtLQulqrXBIh28ZL2CA2Xaro3CNdk6Hle-4aD8_BIh0NqvUYdC3hUGBhGwWz14TdWI15FtIJE-Gxl7qBtQDjHFDziDu9BapWSLsGxfAiGBTxkfjDLIF29EozI3XKqla0Z6SkKw5T4WR12WjemUVwJ364CT3oGAWHHa_m0S7udAyo88Wq-qTzyIp8C80fqpwShxf_9027CF9d8nFNQkXr9KG0NyFdSdU98G2KhLZFlyKRzeS7jO_B8F2GzyVE0A_B-X4Ufin-2TxIeBP3GWoBjVeRx7gmdvsv7pFFMkIzm1OPbEvrLQGWfsHdV3_cGMSwE6q1AwTTJr9-tAMMX85a-65FiOmi8bOdjJ_hEkCusCCk42UeXRXnbGbeLEmKQYxRSLfn_eCApdZPTC3CWyRkJrFxnHHaKIdwu07llyRt2lEWJPMFsKte7nrZcOvDZtAxm-3Dy561YZ9f5orJ5eMJLJGhHwqq56AkJGGwYrGsWMMGZX648fxmPhzrof9fZe2yvZFSsKBa3y-3uvl2CEhOpQi1v47BeiVb3q3R3zc3IDGZ5VVCYF2vZCxCZbaeI0NMmsStX_7XhWSYBI_MKsOBr60Yo6NVQ5erwN5sV8DXCzcN6WdjrlUoTxfTaIiDt9UTSHBftcW0OiGeY55HEGwZMznlHI4VXZLKZDFRkLWEUmegnSDqvHvqyydy_Kha9Kjw6g_AA6xyp7gJ9D28TcDGgdpCnWgxcp0xmmvkT26r7ZvY-k16OJQAMaKQMoO-frIfwCeQIvYORljxL0VGk4YnKTvoSVyXhK6uUgyhnjL24xxKb5ck9YLp3FmvAmJkMS_NZirRExOo9ELgGp7RwMdfGMXEgqd9-0sex2CGegi68jkqi8vZTv81uTavPQtbQj9y0oFVDdBYT1CzA4hJ3JCn3h8rzXuECbTD780HXQ_8YV-bds1Xu7Had9IU3GSbOYE-OYIhAjIXOGdp424U_JPFrM02qR0Vh3uPn4PmvWVgSdOsmxRBAZG_hU44hFaZzbMf4CBK2AvN_pOHHnZAo-eZnqAfJF0pRa7MvjjknuZho1oFTfuczvs8G68T9dwVs08NDfJVsF0gcnd_K0Cssk3S2w78A7wf4SbMc3gPucYmZTCOr6OsRKoPjUc92lBBw2-8Cnw9di3sE7uDDp5O4cmzUJBcH5CBRZcgCC7JPIJc-TuBl0FZnrDY7GE3kKLnYbK-rp9sb7JX2aLYHwBNuDnwtwlIjRAgkj6elV749lNZrAlPzscQNo&prev=RQCB9E4C1BBCD8A7&p=20&pg=182) * Advantest Europe GmbH * Sindelfingen * October 8 Senior ASIC Post-Silicon Validation Engineer develops and aligns test plans for ASICs across analog, RF, power, and high-speed digital. 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jobs in Gelsenkirchen") * 1 ![Herne](/public/img/coa/de.herne.png "Coat of arms of Herne") [Herne](/in/herne/germany "English jobs in Herne") * 1 ![Mülheim](/public/img/coa/de.muelheim-an-der-ruhr.png "Coat of arms of Mülheim") [Mülheim](/in/muelheim-an-der-ruhr/germany "English jobs in Mülheim") * 1 ![Oberhausen](/public/img/coa/de.oberhausen.png "Coat of arms of Oberhausen") [Oberhausen](/in/oberhausen/germany "English jobs in Oberhausen") * 1 ![Offenbach am Main](/public/img/coa/de.offenbach-am-main.png "Coat of arms of Offenbach am Main") [Offenbach am Main](/in/offenbach-am-main/germany "English jobs in Offenbach am Main") * 1 ![Pforzheim](/public/img/coa/de.pforzheim.png "Coat of arms of Pforzheim") [Pforzheim](/in/pforzheim/germany "English jobs in Pforzheim") * 1 ![Remscheid](/public/img/coa/de.remscheid.png "Coat of arms of Remscheid") [Remscheid](/in/remscheid/germany "English jobs in Remscheid") * 1 ![Saarbrücken](/public/img/coa/de.saarbruecken.png "Coat of arms of Saarbrücken") [Saarbrücken](/in/saarbruecken/germany "English jobs in Saarbrücken") * 1 ![Solingen](/public/img/coa/de.solingen.png "Coat of arms of Solingen") [Solingen](/in/solingen/germany "English jobs in Solingen") #### germany in States... * 854 ![Bavaria](/public/img/coa/de.bayern.png "Coat of arms of Bavaria") [Bavaria](/in/bayern/germany "English jobs in Bavaria") * 544 ![Baden-Württemberg](/public/img/coa/de.baden-wuerttemberg.png "Coat of arms of Baden-Württemberg") [Baden-Württemberg](/in/baden-wuerttemberg/germany "English jobs in Baden-Württemberg") * 513 ![North Rhine-Westphalia](/public/img/coa/de.nordrhein-westfalen.png "Coat of arms of North Rhine-Westphalia") [North Rhine-Westphalia](/in/nordrhein-westfalen/germany "English jobs in North Rhine-Westphalia") * 384 ![Lower Saxony](/public/img/coa/de.niedersachsen.png "Coat of arms of Lower Saxony") [Lower Saxony](/in/niedersachsen/germany "English jobs in Lower Saxony") * 364 ![Hesse](/public/img/coa/de.hessen.png "Coat of arms of Hesse") [Hesse](/in/hessen/germany "English jobs in Hesse") * 349 ![Rhineland-Palatinate](/public/img/coa/de.rheinland-pfalz.png "Coat of arms of Rhineland-Palatinate") [Rhineland-Palatinate](/in/rheinland-pfalz/germany "English jobs in Rhineland-Palatinate") * 148 ![Berlin](/public/img/coa/de.berlin.png "Coat of arms of Berlin") [Berlin](/in/berlin/germany "English jobs in Berlin") * 105 ![Schleswig-Holstein](/public/img/coa/de.schleswig-holstein.png "Coat of arms of Schleswig-Holstein") [Schleswig-Holstein](/in/schleswig-holstein/germany "English jobs in Schleswig-Holstein") * 79 ![Hamburg](/public/img/coa/de.hamburg.png "Coat of arms of Hamburg") [Hamburg](/in/hamburg/germany "English jobs in Hamburg") * 69 ![Saxony](/public/img/coa/de.sachsen.png "Coat of arms of Saxony") [Saxony](/in/sachsen/germany "English jobs in Saxony") * 56 ![Brandenburg](/public/img/coa/de.brandenburg.png "Coat of arms of Brandenburg") [Brandenburg](/in/brandenburg/germany "English jobs in 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