13 entry level English-speaking jobs in Aachen

Depending on your experience, there are opportunities to contribute at a technical or leadership level ... : 3–5 years in digital IC design Senior-Level: 6+ years, with track record of IP/block ownership MSc ... ensure seamless integration Develop testbenches and support silicon bring-up and validation (Senior level ... integration and test concepts Independent, detail-oriented, and solutions-driven mindset Qualifications Mid-Level

Create behavioral models and perform architecture-level analyses. ... MSc/PhD in Electrical Engineering, Microelectronics, or related field. 3–5 years’ experience for mid-level

Seniority level Mid-Senior level Employment type Full-time Job function Manufacturing Industries Plastics

customer requirements, industry trends and business requirements• Escalate critical issues to high level ... skills• 8+ years’ experience with TCP/IP protocol stack, IPv4-IPv6, DHCP, PXE and other application-level ... Develop training sessions to ensure sales awareness on Supermicro system solution offering• Provide 3rd level

with strong project management and cross-functional collaboration skills.Employment detailsSeniority level

Seniority level Director Employment type Employment type Full-time Job function Job function Quality ... quality control operations and standardization ______________________________________ Seniority level

amazing opportunity to work for a prestigious global brand and on challenging and complex enterprise level

Strong understanding of system-level integration, test methodologies, and post-silicon validation.

Collaborate with partners and customers on a technical level to define and develop the next generation

Mentor and support junior and mid-level engineers, fostering a culture of growth and collaboration.

and methodologies across the IC design flow (Cadence, Synopsys, etc.).Strong understanding of system-level

Status and progress 3rd Level support on complex customer problems Ensure regular reporting wrt.

and methodologies across the IC design flow (Cadence, Synopsys, etc.).Strong understanding of system-level