52 ux stepstone germany English-speaking jobs in Aachen

SAP WM/EWM Consultant for international S/4HANA projects. Responsibilities include implementing and customizing SAP WM/EWM solutions, analyzing logistics processes, and supporting testing and go-live phases. Requires 2+ years of SAP WM and/or EWM experience.

Conduct a Bachelor's Thesis on Stress Analysis of USP Laser Structuring in Sapphire. Plan and conduct experiments on the SLE laser processing system and measure stress distributions.

Experienced barbers sought for full-time, permanent positions in Nordic partner barbershops. Offer includes competitive salaries starting at 3,000 EUR per month gross, flight ticket coverage, relocation support, and opportunities for professional growth.

Senior Director IT to build and lead the IT organization and technology foundation. Responsibilities include enterprise IT, cybersecurity, data, AI, and architecture strategy. Requires proven senior IT leadership in high-tech environments.

Design and develop firmware and software for wireless modules like Wi-Fi, Bluetooth, and LTE/5G. Responsibilities include driver development for Embedded Linux/Android and RF hardware bring-up. Requires C/C++ skills and experience in embedded systems.

Design, simulate, and validate high-speed analog transmitter and receiver circuits for next-generation Optical Compute Interconnect products. Develop power-efficient analog front ends interfacing with integrated photonic devices.

Own packaged product reliability, defining mission profiles and failure mechanisms. Develop qualification strategies, lead failure analysis, and provide data-driven release recommendations for semiconductor packages.

Lead Plating Process Engineer for next-gen materials like graphene. Oversee fab startup, tool qualification, and process ramp-up for advanced plating processes. Requires 5+ years in semiconductor plating engineering.

Lead CMP Process Engineer developing processes for 2D materials and novel architectures. Key tasks include fab startup, tool qualification, defining process specifications, and establishing Process of Record. Requires 5+ years in semiconductor process engineering with CMP focus.

Execute product qualification activities, turning plans into test setups and traceable evidence for product release. Develop test hardware, run bench/lab tests (thermal, electrical, mechanical), and coordinate campaigns with external partners.

Senior People Development Partner to embed a high-performance culture. Partner with managers on development, performance reviews, and career progression. Requires 6-10 years in HR Business Partnering with strong coaching skills.

Own the complete tape-out flow for Electronic-Photonics ICs, managing GDS integration, mask data preparation, and DfX co-integration on a 300mm platform. Requires expertise in GDSII, DRC/LVS/ERC, and production flows.

Senior High-Speed Analog/RF System Architect to own SerDes architecture for graphene photonic interconnect SoCs. Define electrical architecture for PLL, TIAs, drivers, equalizers, ADC/DACs, and CDR, targeting 112G/224G+ PAM4.

Own the hardware architecture of a next-gen hybrid compute engine combining electronic and photonic compute. Define compute architecture, memory hierarchy, and data fabric, bridging compute, heterogeneous system design, and electronic-photonic co-design.

Senior Equipment Engineer for Electrochemical Plating to lead tool planning and installation at a semiconductor fab. Requires 5+ years' experience with plating equipment, tool installation, and knowledge of deposition and bath chemistry.

CD-SEM Expert needed to operate, optimize, and maintain metrology tools for nanoscale measurements on semiconductor wafers. This role enables process control and yield improvement by translating critical dimension data. Requires 5+ years in semiconductor manufacturing.

Senior Wet Cleaning Process Engineer to lead wet clean process development and scaling for Black FabONE. Focus on 2D material preparation, tool validation, and establishing Process of Record. Requires 5+ years in semiconductor process engineering.

Senior Platform & Hardware Applications Engineer to enable customer adoption of Optical Compute Interconnect technology. Responsibilities include system validation, reference design, and technical support for high-speed hardware.

Oversee ASIC programs combining electronics and photonics in advanced chiplet packages. Lead cross-functional teams, manage the silicon cycle from concept to release, and coordinate external IP providers to meet technical and schedule targets.

Lead tool installation and reliability planning for wet cleaning in a cleanroom facility. Responsibilities include equipment planning, integration, and supporting yield improvement. Requires 5+ years of wet cleaning experience in semiconductor manufacturing.