Familiar with design, simulation, synthesis, place and route design skills FPGA implementation, routing.., design constraints, timing and pin-out skills Troubleshooting RTL Design Flaws using Simulation Environment..Required Qualifications: 5+ years of industry experience VHDL design skills to implement communication..Familiar with DAL-A design methodology Technologies & Tools: Familiarity with General lab equipment Lab..I/O Timing Analysis Developing DO254 related documents including but not limited to: requirements, design