31 sap germany English-speaking jobs in Erlangen

  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
  • Friedrich-Alexander-Universität Erlangen-Nürnberg
  • Erlangen, , Germany
  • August 8
Your Tasks Integrated hardware accelerators for machine learning in RISC-V subsystems Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a Syste
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