1008 ux stepstone+germany English-speaking jobs in North Rhine-Westphalia

Senior Integration Engineer develops robust integration solutions for complex enterprise environments, including hybrid cloud architectures. Requires 10–15 years of experience, knowledge of Docker/Kubernetes, and strong analytical skills.

Senior Platform & Hardware Applications Engineer to enable customer adoption of Optical Compute Interconnect technology. Responsibilities include platform integration, system validation, reference design, and technical support for high-speed hardware.

Oversee ASIC programs combining electronics and photonics in advanced chiplet packages. Lead cross-functional teams, manage external IP providers, and drive the silicon program cycle from concept to release.

Own the hardware architecture of a next-gen hybrid compute engine combining electronic and photonic compute. Define compute architecture, memory hierarchy, and system interfaces for dynamic workload execution.

Associate Consultant in Cost and Value Management performs cost analysis of technical products and components. Responsibilities include cost evaluations for target costing and identifying cost reduction potentials. Requires an engineering or industrial engineering degree.

Experienced Electronic-Photonics IC Mask Data Preparation & GDS Data Integration Engineer to own the tape-out flow. Drive EIC+PIC DfX across a 300mm graphene photonics platform, managing GDS integration and mask release.

Senior High-Speed Analog/RF System Architect to own SerDes architecture for graphene photonic interconnect SoCs. Define electrical architecture for PLL, TIAs, drivers, equalizers, ADC/DACs, and CDR, targeting 112G/224G+ PAM4.

Senior Wet Cleaning Process Development Engineer to lead wet clean process development and scaling for Black FabONE. Focus on 2D material preparation, tool validation, and establishing Process of Record. Requires 5+ years in semiconductor wet cleaning.

Product Qualification Engineer executes product qualification activities, turning plans into test setups and traceable evidence for product release. Requires 2-4+ years of hardware bring-up/qualification experience, including RF/high-speed I/O testing.

Lead tool installation and reliability planning for wet cleaning in a cleanroom facility. Responsibilities include equipment planning, integration, and supporting yield improvement in semiconductor manufacturing.

Senior ATE Test Engineer to own 300mm wafer test infrastructure bring-up and operation. Develop/debug test programs for DC, RF, and electro-optical characterization, and drive probe card design.

Design, simulate, and validate high-speed analog transmitter and receiver circuits for next-generation Optical Compute Interconnect products. Develop power-efficient analog front ends interfacing with integrated photonic devices.

CD-SEM Expert needed to operate, optimize, and maintain metrology tools for nanoscale measurements on semiconductor wafers. This role supports process control, yield improvement, and advanced node development.

Senior People Development Partner to embed a high-performance culture. Partner with managers on performance, talent processes, and career growth. Requires 6-10 years in HR Business Partnering with strong coaching skills.

Defect Inspection Engineer ensures defect-free semiconductor wafers using AOI and unpatterned inspection. Responsibilities include setting up, optimizing recipes, and analyzing defect data to improve process flow. Requires 5+ years in semiconductor inspection.

PIC Layout Engineer to support photonic integrated circuit layout development. Responsibilities include maintaining layout infrastructure, running DRC/LVS, and implementing design rules. Requires a relevant degree and strong Python skills.

Lead CMP process development for next-gen materials like 2D materials. Oversee fab startup, tool qualification, and establishing Process of Record. Requires 5+ years in semiconductor process engineering with CMP focus.

Lead development and optimization of graphene transfer, lamination, and wet processes for next-gen IGP devices. Drive process innovation from R&D through manufacturing ramp-up, integrating equipment and improving yield.

Lead technical direction for next-gen AI software platforms across embedded and edge computing. Drive AI software architecture, model deployment, compiler ecosystems, and hardware/software co-design. Requires deep expertise in AI, compilers, and heterogeneous systems.

Principal EDA Engineer provides technical leadership for global engineering compute and design-data-management environments. Responsibilities include managing Perforce/IPLM, developing automation, and supporting CAD infrastructure.