57 germany English-speaking jobs in Aachen

Senior High-Speed Analog/RF System Architect to own SerDes architecture for graphene photonic interconnect SoCs. Define electrical architecture for PLL, TIAs, drivers, equalizers, ADC/DACs, and CDR, targeting 112G/224G+ PAM4.

Senior Wet Cleaning Process Development Engineer to lead wet clean process development and scaling for Black FabONE. Focus on 2D material preparation, tool validation, and establishing Process of Record. Requires 5+ years in semiconductor wet cleaning.

Product Qualification Engineer executes product qualification activities, turning plans into test setups and traceable evidence for product release. Requires 2-4+ years of hardware bring-up/qualification experience, including RF/high-speed I/O testing.

Lead tool installation and reliability planning for wet cleaning in a cleanroom facility. Responsibilities include equipment planning, integration, and supporting yield improvement in semiconductor manufacturing.

Senior ATE Test Engineer to own 300mm wafer test infrastructure bring-up and operation. Develop/debug test programs for DC, RF, and electro-optical characterization, and drive probe card design.

Design, simulate, and validate high-speed analog transmitter and receiver circuits for next-generation Optical Compute Interconnect products. Develop power-efficient analog front ends interfacing with integrated photonic devices.

Associate Consultant in Cost and Value Management performs cost analysis of technical products and components. Responsibilities include cost evaluations for target costing and identifying cost reduction potentials. Requires an engineering or industrial engineering degree.

Lead Plating Process Engineer for next-gen materials like graphene. Responsibilities include developing plating processes, managing fab startup activities, and establishing Process of Record. Requires 5+ years in semiconductor plating engineering.

CD-SEM Expert needed to operate, optimize, and maintain metrology tools for nanoscale measurements on semiconductor wafers. This role supports process control, yield improvement, and advanced node development.

Own packaged product reliability, defining mission profiles and failure mechanisms. Assess risks across substrates, interconnect, and solder joints. Execute qualification plans per JEDEC, AEC-Q100/Q006, and drive root-cause analysis.

Senior Equipment Engineer for Electrochemical Plating to lead tool planning and installation at a semiconductor fab. Responsibilities include equipment selection, vendor management, and process qualification for advanced interconnect technologies.

Senior People Development Partner to embed a high-performance culture. Partner with managers on performance, talent processes, and career growth. Requires 6-10 years in HR Business Partnering with strong coaching skills.

Defect Inspection Engineer ensures defect-free semiconductor wafers using AOI and unpatterned inspection. Responsibilities include setting up, optimizing recipes, and analyzing defect data to improve process flow. Requires 5+ years in semiconductor inspection.

PIC Layout Engineer to support photonic integrated circuit layout development. Responsibilities include maintaining layout infrastructure, running DRC/LVS, and implementing design rules. Requires a relevant degree and strong Python skills.

Lead CMP process development for next-gen materials like 2D materials. Oversee fab startup, tool qualification, and establishing Process of Record. Requires 5+ years in semiconductor process engineering with CMP focus.

Own schematic capture and physical layout of photonic integrated circuits. Translate device concepts into PDK-compliant, tape-out-ready PIC blocks. Drive circuit-level implementation and verification.

Lead development and optimization of graphene transfer, lamination, and wet processes for next-gen IGP devices. Drive process innovation from R&D through manufacturing ramp-up, integrating equipment and improving yield.