820 English-speaking jobs in Baden-Württemberg

Senior ASIC Design Engineer will develop digital modules and subsystems for semiconductor testing. Responsibilities include design, RTL coding, verification, and test structure generation. Requires a BS in Electrical Engineering/Physics/Computer Science and 5+ years of experience in Design for Test and BIST.

Senior ASIC Design Engineer will develop digital modules and subsystems for semiconductor testing. Responsibilities include design, RTL coding, verification, and test structure generation. Requires a BS in Electrical Engineering/Physics/Computer Science and 5+ years of experience in Design for Test and BIST.

Senior ASIC Design Engineer will develop digital modules and subsystems for semiconductor testing. Responsibilities include design, RTL coding, verification, and test structure generation. Requires a BS in Electrical Engineering/Physics/Computer Science and 5+ years of experience in Design for Test and BIST.

Senior ASIC Design Engineer will develop digital modules and subsystems for semiconductor testing. Responsibilities include architecture development, RTL coding, verification, and design for test implementation. Requires a BS in Electrical Engineering/Physics/Computer Science and 5+ years of experience in Design for Test and BIST.

Senior ASIC Design Engineer will develop digital modules and subsystems for semiconductor testing. Responsibilities include design, RTL coding, verification, and test structure generation. Requires a BS in Electrical Engineering/Physics/Computer Science and 5+ years of experience in Design for Test and BIST.

Senior ASIC Design Engineer will develop digital modules and subsystems for semiconductor testing. Responsibilities include design, RTL coding, verification, and test structure generation. Requires a BS in Electrical Engineering/Physics/Computer Science and 5+ years of experience in Design for Test and BIST.

Senior ASIC Design Engineer will develop digital modules and subsystems for semiconductor testing. Responsibilities include design, RTL coding, verification, and test structure generation. Requires a BS in Electrical Engineering/Physics/Computer Science and 5+ years of experience in Design for Test and BIST.

Senior Digital ASIC Design Engineer will develop and verify digital modules and subsystems for Advantest's semiconductor testing solutions. Responsibilities include requirements gathering, architecture development, RTL coding, and verification at the module and chip level.

Senior Digital ASIC Design Engineer will develop and verify digital modules and subsystems for Advantest's semiconductor testing solutions. Responsibilities include requirements gathering, architecture development, RTL coding, and verification at the module and chip level.

Senior Digital ASIC Design Engineer will develop and verify digital modules and subsystems for Advantest's semiconductor testing solutions. Responsibilities include requirements gathering, architecture development, RTL coding, and verification at the module and chip level.

Senior Digital ASIC Design Engineer will develop and verify digital modules and subsystems for Advantest's semiconductor testing solutions. Responsibilities include requirements gathering, architecture development, RTL coding, and verification.

Senior Digital ASIC Design Engineer will develop and verify digital modules and subsystems for Advantest's semiconductor testing solutions. Responsibilities include requirements gathering, architecture development, RTL coding, and verification at the module and chip level.

Senior Digital ASIC Design Engineer will develop and verify digital modules and subsystems for Advantest's semiconductor testing solutions. Responsibilities include requirements gathering, architecture development, RTL coding, and verification.

ETH Zurich seeks tenured faculty in Artificial Intelligence and its Mathematical and Computational Foundations. Successful candidates will establish and lead a research group, contribute to teaching and student supervision, and collaborate with partners in Germany, Switzerland, and internationally.

Leads the preparation, analysis, and review of consolidated financial statements for the ZEISS Group, ensuring compliance with IFRS and internal policies. Serves as the main point of contact for consolidation matters and drives digital transformation of group consolidation activities.

Design and continuously improve end-to-end inventory management processes for raw materials, work-in-progress, and finished goods inventory. Develop and maintain buffer inventory levels, define KPIs, analyze data, and ensure compliance with internal controls and regulatory standards. Collaborate with stakeholders to implement and improve inventory management processes.

Senior ASIC Design Engineer will develop digital modules and subsystems for semiconductor testing. Responsibilities include design, RTL coding, verification, and test pattern generation. Requires experience in Design for Test, BIST, and simulation tools.

Build and operate shared AI infrastructure and developer platforms to enable AI for all engineers. Design, ship, and own LLM-powered services, including conversational flows and RAG-based applications.

Salesforce Architect needed to design and implement end-to-end Salesforce solutions, including Sales Cloud, Service Cloud, Experience Cloud, and Revenue Cloud. Lead technical initiatives, mentor developers, and ensure compliance with security and integration standards.

Senior Digital ASIC Design Engineer Verification will design and code digital modules and subsystems for semiconductor testing. Responsibilities include requirements gathering, RTL coding, verification, and documentation. Requires a university degree in EE, experience with ASIC design methodologies, and proficiency in Verilog and SystemVerilog.