54 English-speaking jobs in Aachen

Your Job Synthesis of NiAl LDH as precursors for Ni/γ-Al₂O₃ catalysts Optimization of the synthesis and reaction parameters Complementary characterization using PXRD, PDF, TGA-MS, DRIFT-FTIR, and N₂ physisorption Data analysis using Python, OriginPro … Literature review and interpretation of results The topic offers various focuses and can be adapted based on your interests Your Profile C

Support the EMEA commercial organization by managing the sales process from PO receipt through invoicing and revenue recognition. Coordinate with Sales, Finance, and Logistics to ensure accurate order processing and timely fulfillment.

Drive growth for Hexagon Mining in Europe by identifying and developing new business opportunities. This customer-facing role requires strong B2B sales skills, technical understanding of mining solutions, and experience managing complex sales cycles.

Senior High-Speed Analog/RF System Architect to own SerDes architecture for graphene photonic interconnect SoCs. Define electrical architecture for PLL, TIAs, drivers, equalizers, ADC/DACs, and CDR, targeting 112G/224G+ PAM4.

Lead tool installation and reliability planning for wet cleaning in a cleanroom facility. Responsibilities include equipment planning, integration, and supporting yield improvement. Requires 5+ years of wet cleaning experience in semiconductor manufacturing.

Lead Plating Process Engineer for next-gen materials like graphene. Oversee fab startup, tool qualification, and process ramp-up for advanced plating processes. Requires 5+ years in semiconductor plating engineering.

Senior People Development Partner to embed a high-performance culture. Partner with managers on development, performance reviews, and career progression. Requires 6-10 years in HR Business Partnering with strong coaching skills.

Execute product qualification activities, turning plans into test setups and traceable evidence for product release. Develop test hardware, run bench/lab tests (thermal, electrical, mechanical), and coordinate campaigns with external partners.

Own packaged product reliability, defining mission profiles and failure mechanisms. Develop qualification strategies, lead failure analysis, and provide data-driven release recommendations for semiconductor packages.

Senior Platform & Hardware Applications Engineer to enable customer adoption of Optical Compute Interconnect technology. Responsibilities include system validation, reference design, and technical support for high-speed hardware.

CD-SEM Expert needed to operate, optimize, and maintain metrology tools for nanoscale measurements on semiconductor wafers. This role enables process control and yield improvement by translating critical dimension data. Requires 5+ years in semiconductor manufacturing.

Oversee ASIC programs combining electronics and photonics in advanced chiplet packages. Lead cross-functional teams, manage the silicon cycle from concept to release, and coordinate external IP providers to meet technical and schedule targets.

Own electrical characterization and co-design of advanced packages. Drive package-level electrical signoff by developing equivalent circuit models and leading SI/PI analysis for high-speed interconnect requirements.

Senior Equipment Engineer for Electrochemical Plating to lead tool planning and installation at a semiconductor fab. Requires 5+ years' experience with plating equipment, tool installation, and knowledge of deposition and bath chemistry.

Design, simulate, and validate high-speed analog transmitter and receiver circuits for next-generation Optical Compute Interconnect products. Develop power-efficient analog front ends interfacing with integrated photonic devices.

Own the complete tape-out flow for Electronic-Photonics ICs, managing GDS integration, mask data preparation, and DfX co-integration on a 300mm platform. Requires expertise in GDSII, DRC/LVS/ERC, and production flows.

Own the hardware architecture of a next-gen hybrid compute engine combining electronic and photonic compute. Define compute architecture, memory hierarchy, and data fabric, bridging compute, heterogeneous system design, and electronic-photonic co-design.

Senior Wet Cleaning Process Engineer to lead wet clean process development and scaling for Black FabONE. Focus on 2D material preparation, tool validation, and establishing Process of Record. Requires 5+ years in semiconductor process engineering.

Experienced Process Integration Engineer needed to develop stable, scalable process integration solutions for integrated graphene photonics and high-speed optical chip interconnect interconnect. Requires MSc/PhD and 7+ years in semiconductor fab process integration.

Lead CMP Process Engineer developing processes for 2D materials and novel architectures. Key tasks include fab startup, tool qualification, defining process specifications, and establishing Process of Record. Requires 5+ years in semiconductor process engineering with CMP focus.